公开(公告)号：US20240274676A1

公开(公告)日：2024-08-15

申请号：US18221693

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin LEE ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; a 1st source/drain region on the channel structure; and an enlarged backside contact structure connected to the 1st source/drain region, wherein the enlarged backside contact structure includes a backside contact structure below the 1st source/drain region, a 1st side via structure at a 1st side of the 1st source/drain region, and a 1st front contact structure above the 1st source/drain region, and wherein the backside contact structure is connected to the 1st side via structure, which is connected to the front contact structure.

公开(公告)号：US20230326926A1

公开(公告)日：2023-10-12

申请号：US17841299

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WookHyun KWON ,  Byounghak HONG ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes: a substrate; a lower field-effect transistor including a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1st and 2nd source/drain regions; and an upper field-effect transistor, on the lower field-effect transistor, including an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3rd and 4th source/drain regions vertically above the 1st and 2nd source/drain regions, respectively, wherein the 1st source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3rd source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2nd source/drain region and a bottom portion the 4th source/drain region are connected to each other.

公开(公告)号：US20250040303A1

公开(公告)日：2025-01-30

申请号：US18775217

申请日：2024-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghak KIM ,  Punjae CHOI ,  Sooyoung PARK ,  Shigeru INOUE

IPC: H01L33/32 ,  H01L25/075 ,  H01L33/02 ,  H01L33/04 ,  H01L33/14

Abstract: A light emitting element is provided. The light emitting element includes: a light emitting stack including an active layer between an N-type nitride semiconductor layer and a P-type nitride semiconductor layer, the light emitting stack having a width of 5 nm or more and 200 μm or less; a first electrode connected to the N-type nitride semiconductor layer; and a second electrode connected to the P-type nitride semiconductor layer. The P-type nitride semiconductor layer has a first surface, adjacent to the active layer, and a second surface, opposite to the first surface, and includes AlxInyGazN (0≤x

公开(公告)号：US20240104723A1

公开(公告)日：2024-03-28

申请号：US18112927

申请日：2023-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gahee KIM ,  Joon-Kee CHO ,  Hyun Do CHOI ,  Younsuk CHOI ,  Jeonghun KIM ,  Sooyoung PARK

IPC: G06T7/00 ,  G06V10/25 ,  G06V10/28 ,  G06V10/62

CPC classification number: G06T7/0012 ,  G06V10/25 ,  G06V10/28 ,  G06V10/62

Abstract: An apparatus for measuring solubility includes: a display configured to display at least one patterned background image; an image obtaining sensor configured to obtain at least one transmission image formed by light from the at least one patterned background image being transmitted through a container accommodating a target sample, of which solubility is to be measured; and a processor configured to analyze a degree of dissolution of the target sample from the at least one transmission image based on at least one analysis algorithm.

公开(公告)号：US20230275084A1

公开(公告)日：2023-08-31

申请号：US17738743

申请日：2022-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/50

CPC classification number: H01L27/0629 ,  H01L27/0688 ,  H01L21/823475 ,  H01L21/8221 ,  H01L23/50

Abstract: Provided is a semiconductor device that includes: at least one field-effect transistor and at least one PN junction device at a lateral side of the at least one field-effect transistor in a 1st layer; and at least one back side power delivery network (BSPDN) structure in a 2nd layer below the 1st layer, wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.

公开(公告)号：US20230352528A1

公开(公告)日：2023-11-02

申请号：US17945695

申请日：2022-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok PARK ,  Sooyoung PARK ,  Kang-ill SEO ,  Jaehong LEE

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/0847 ,  H01L27/0924

Abstract: Provided is a multi-stack semiconductor device including: a substrate; a lower-stack nanosheet transistor including two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and including two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions, wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of: a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers; and a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers.