公开(公告)号：US20250167110A1

公开(公告)日：2025-05-22

申请号：US18617033

申请日：2024-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Hyo Jong SHIN ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device based on a cell block which may include: a 1st cell comprising a 1st lower active region and a 1st upper active region above the 1st lower active region in a 3rd direction, both being extended in a 1st direction; a 2nd cell comprising a 2nd lower active region and a 2nd upper active region above the 2nd lower active region in the 3rd direction, both being extended in the 1st direction; and a cell spacer between the 1st cell and the 2nd cell in a 2nd direction, wherein no active region is formed in the cell spacer.

公开(公告)号：US20250159986A1

公开(公告)日：2025-05-15

申请号：US18639141

申请日：2024-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-min JUNG ,  Kang-ill SEO

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes: a 1st active region extended in a 1st direction and including: a 1st out-corner edge at which a width of the 1st active region in a 2nd direction gradually changes along the 1st direction; and a 1st in-corner edge at which the width of the 1st active region less gradually changes along the 1st direction than at the 1st out-corner edge; and a gate structure extended in the 2nd direction and overlapping the 1st out-corner edge in a 3rd direction, wherein the 1st direction horizontally intersects the 2nd direction, and the 3rd direction vertically intersects the 1st direction and the 2nd direction.

公开(公告)号：US20250022797A1

公开(公告)日：2025-01-16

申请号：US18378789

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Janggeun LEE ,  Wonhyuk HONG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes: a frontside structure including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line on the frontside structure; and a 2nd metal line on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction, and the 1st metal line and the 2nd metal line have an equal height.

公开(公告)号：US20240162309A1

公开(公告)日：2024-05-16

申请号：US18135530

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung YANG ,  Myunghoon JUNG ,  Seungmin SONG ,  Seungchan YUN ,  Sejung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.

公开(公告)号：US20250120183A1

公开(公告)日：2025-04-10

申请号：US18954980

申请日：2024-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghoon JUNG ,  Jaehong LEE ,  Seungchan YUN ,  Kang-ill SEO

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

公开(公告)号：US20240274676A1

公开(公告)日：2024-08-15

申请号：US18221693

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin LEE ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; a 1st source/drain region on the channel structure; and an enlarged backside contact structure connected to the 1st source/drain region, wherein the enlarged backside contact structure includes a backside contact structure below the 1st source/drain region, a 1st side via structure at a 1st side of the 1st source/drain region, and a 1st front contact structure above the 1st source/drain region, and wherein the backside contact structure is connected to the 1st side via structure, which is connected to the front contact structure.

公开(公告)号：US20240023326A1

公开(公告)日：2024-01-18

申请号：US17977575

申请日：2022-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seungchan YUN ,  Jaehong LEE ,  Kang-ill SEO

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: Provided is a multi-stack nanosheet structure that includes: at least a first nanosheet structure and at least a second nanosheet structure, above the substrate, separated from each other, wherein the first nanosheet structure and second nanosheet structure are adjacent to each other; a channel structure comprising a first portion on the first nanosheet structure, a second portion on the second nanosheet structure, and a third portion on the substrate between the first and second portions, wherein the first portion, the second portion and the third portion form a single continuous structure; a gate structure between the first and second portions on the third portion of the channel structure, wherein the gate structure comprises a gate dielectric layer comprising oxide; and at least a first source/drain region on the first nanosheet structure, and at least a second source/drain region on the second nanosheet structure, wherein the first source/drain region and the second source/drain region include an n-type or p-type dopant.

公开(公告)号：US20230343839A1

公开(公告)日：2023-10-26

申请号：US17885237

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Sung KIM ,  Jaejik BAEK ,  Wonhyuk HONG ,  Myunghoon JUNG ,  Jongjin LEE ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L29/401 ,  H01L29/0673

Abstract: Provided is a semiconductor device that includes: at least one transistor, a front side structure, and a back side structure, the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the back side structure, wherein the front via is formed in a via hole formed of a lower via hole and an upper via hole vertically connected to each other, and wherein the via hole has a bent structure at a side surface thereof where the lower via hole is connected to the upper via hole.

公开(公告)号：US20230326926A1

公开(公告)日：2023-10-12

申请号：US17841299

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WookHyun KWON ,  Byounghak HONG ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes: a substrate; a lower field-effect transistor including a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1st and 2nd source/drain regions; and an upper field-effect transistor, on the lower field-effect transistor, including an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3rd and 4th source/drain regions vertically above the 1st and 2nd source/drain regions, respectively, wherein the 1st source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3rd source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2nd source/drain region and a bottom portion the 4th source/drain region are connected to each other.

公开(公告)号：US20250142871A1

公开(公告)日：2025-05-01

申请号：US18617125

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong LEE ,  Jintae KIM ,  Myung YANG ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes a 1st source/drain region; and a 1st contact structure on a 1st portion of the 1st source/drain region; and a 2nd contact structure on a 2nd portion of the 1st source/drain region, wherein at least one of the 1st contact structure and the 2nd contact structure is configured to connect the 1st source/drain region to a voltage source or another circuit element for signal routing.