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    CELL ARCHITECTURE WITH IMPROVED BACKSIDE POWER RAIL THROUGH ENGINEERING CHANGE ORDER
    1.
    发明申请
    CELL ARCHITECTURE WITH IMPROVED BACKSIDE POWER RAIL THROUGH ENGINEERING CHANGE ORDER 有权

    公开(公告)号：US20240413160A1

    公开(公告)日：2024-12-12

    申请号：US18382301

    申请日：2023-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jintae KIM ,  Kang-ill Seo

    IPC: H01L27/118

    Abstract: A semiconductor device includes: a plurality of cells including 1st cells arranged in a 1st row of a layout of the semiconductor device; and a 1st backside power rail and a 2nd backside power rail disposed below the 1st cells, extended in a 1st direction, and arranged in a 2nd direction intersecting the 1st direction, wherein the 1st backside power has a 1st width, and the 2nd backside power rail has a 2nd width which is different from the 1st width.

    ANALOG-TO-DIGITAL CONVERTER AND OPERATING METHOD THEREOF
    2.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230021819A1

    公开(公告)日：2023-01-26

    申请号：US17871538

    申请日：2022-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoungwon LEE ,  Jintae KIM ,  Sungwon ROH

    IPC: H03M1/36

    Abstract: An analog-to-digital converter (ADC) for converting an analog signal into a digital signal includes an amplifier circuit configured to receive the analog signal, and to generate a plurality of amplifier signals by amplifying the analog signal; a comparison circuit configured to compare a plurality of voltage levels corresponding to the plurality of amplifier signals with a positive reference voltage level and a negative reference voltage level, and to output conversion target signals based on a result of the comparison; and a converter circuit configured to convert the conversion target signals into a plurality of digital signals.

    SEMICONDUCTOR CELL ARCHITECTURE INCLUDING BACKSIDE POWER RAILS
    4.
    发明公开
    SEMICONDUCTOR CELL ARCHITECTURE INCLUDING BACKSIDE POWER RAILS 审中-公开

    公开(公告)号：US20240304520A1

    公开(公告)日：2024-09-12

    申请号：US18226338

    申请日：2023-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jintae KIM ,  Panjae PARK

    IPC: H01L23/48

    CPC classification number: H01L23/481

    Abstract: Provided is a semiconductor cell architecture which includes a plurality of cells, a plurality of backside power rails, and a plurality of metal lines, wherein the backside power rails are extended in a cell-length direction, and at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view.

    CELL ARCHITECTURE WITH CENTER-LINE POWER RAILS FOR STACKED FIELD-EFFECT TRANSISTORS
    5.
    发明公开
    CELL ARCHITECTURE WITH CENTER-LINE POWER RAILS FOR STACKED FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20240145343A1

    公开(公告)日：2024-05-02

    申请号：US18133872

    申请日：2023-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Panjae PARK ,  Jintae KIM ,  Hyoeun PARK ,  Kang-Ill SEO

    IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

    CPC classification number: H01L23/481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

    Abstract: A cell architecture including at least one semiconductor device cell is provided. The cell includes: a 1st active pattern and a 2nd active pattern extended in a 1st direction, the 1st active pattern at least partially overlapping the 2nd active pattern in a 3rd direction intersecting the direction; a plurality of gate structures extended in a 2nd direction across the 1st and 2nd active patterns, the 2nd direction intersecting the 1st direction and the 3rd direction; a plurality of metal lines in at least one metal layer of the cell, the metal lines being extended in the 1st direction, and at least one of the metal lines being connected to at least one of the 1st and 2nd active patterns and the gate structures; and at least one power rail connecting the at least one of the 1st and 2nd active patterns to at least one voltage source, wherein the at least one power rail is disposed to be closer to a virtual horizontal center line of the cell extended in the 1st direction than an upper boundary or a lower boundary of the cell.

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