公开(公告)号：US12080332B2

公开(公告)日：2024-09-03

申请号：US17834320

申请日：2022-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungki Hong

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C11/40622

Abstract: An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.

公开(公告)号：US11574671B2

公开(公告)日：2023-02-07

申请号：US17346633

申请日：2021-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Hong ,  Wonil Bae ,  Heonsu Jeong

IPC: G11C11/34 ,  G11C16/06 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4094

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

公开(公告)号：US12027194B2

公开(公告)日：2024-07-02

申请号：US18093473

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungki Hong ,  Geuntae Park

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

公开(公告)号：US12002502B2

公开(公告)日：2024-06-04

申请号：US17882242

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungki Hong

IPC: G11C11/406 ,  G11C29/00

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C29/783

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.

公开(公告)号：US12236994B2

公开(公告)日：2025-02-25

申请号：US18413924

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Bang ,  Seungki Hong

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.

公开(公告)号：US12198751B2

公开(公告)日：2025-01-14

申请号：US18118235

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Hong

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory device and a method of precharging a decoded address are provided. The memory device includes a memory cell array comprising a plurality of rows; a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and an interface circuit configured to: generate the decoded row address based on decoding a plurality of bits of a row address, transfer the decoded row address to the row decoder, in a first mode of the memory device, precharge the decoded row address that is transferred to the row decoder, and in a second mode of the memory device, determine whether a precharge signal is received in the second mode, and precharge the decoded row address based on the precharge signal.

公开(公告)号：US20250013746A1

公开(公告)日：2025-01-09

申请号：US18534135

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongha KIM ,  Seungki Hong ,  Youngjae Park ,  Dohan Kim

IPC: G06F21/56 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.

公开(公告)号：US20240404579A1

公开(公告)日：2024-12-05

申请号：US18539472

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Hong ,  Sanghak Shin

IPC: G11C11/408 ,  G11C11/4074

Abstract: A memory device, which may include: a memory cell array including a plurality of memory cell groups; an intermediate block configured to decode a row address, and configured to output an active block flag and a decoded row address; and a row decoder configured to select a wordline of a plurality of wordlines connected to the memory cell array based on the active block flag and the decoded row address. The row decoder may be configured to convert a portion of the row decoder from an inactive state to an active state to activate a selected memory cell group from among the plurality of memory cell groups based on a received active request, the selected memory group corresponding to the active block flag, and the row decoder may be configured to select the wordline connected to the selected memory cell group based on the decoded row address.

公开(公告)号：US20240062806A1

公开(公告)日：2024-02-22

申请号：US18303522

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Hong ,  Jinsol Park ,  Jaeseong Lim ,  Minsoo Jang ,  Eunki Hong

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094

Abstract: A method of operating a memory device includes precharging a pair of true and complementary bit lines (BL/BLB) to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines (SABL/SABLB) to the equivalent voltage, and then transferring charge associated with offset noise from BL to SABLB concurrently with transferring charge associated with the offset noise from BLB to SABL, so that a voltage difference is established between the SABL and SABLB. Next, a logic state of a memory cell connected to BI is read by transferring charge between the memory cell and BL, concurrently with equilibrating voltages on SABL and SABLB. Then, a voltage difference between SABL and SABLB is sensed and amplified in response to activating an amplifier circuit within the sense amplifier.

公开(公告)号：US11908507B2

公开(公告)日：2024-02-20

申请号：US17722652

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Bang ,  Seungki Hong

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/40615 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/40622

Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.