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公开(公告)号：US11101231B2
公开(公告)日：2021-08-24
申请号：US16819851
申请日：2020-03-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-youn Kim , Seok-hyun Lee , Youn-ji Min , Kyoung-lim Suk , Seok-won Lee
IPC: H01L21/48 , H01L23/00 , H01L23/522 , H01L23/528 , H01L23/31 , H01L21/683 , H01L25/065 , H01L23/498
Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.
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公开(公告)号：US20140077382A1
公开(公告)日：2014-03-20
申请号：US14083733
申请日：2013-11-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Heung-kyu Kwon , Seok-won Lee , Hyon-chol Kim , Su-chang Lee , Chi-young Lee
CPC classification number: H01L24/17 , H01L22/12 , H01L22/20 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/00 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
Abstract translation: 半导体封装可以包括具有第一表面和第二表面的衬底本体。 半导体芯片可以安装在第一表面上，并且多个电极焊盘可以在第二表面上并且选择性地形成为具有从基板主体的中心区域朝向基板主体的外边缘延伸的逐渐变小或更大的尺寸 在半导体封装的回流焊工艺翘曲曲线上。
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Patent Agency Ranking
公开(公告)号：US11086345B2
公开(公告)日：2021-08-10
申请号：US16935610
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok-won Lee , Nam-seog Kim
IPC: G05F1/575
Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.
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公开(公告)号：US09048168B2
公开(公告)日：2015-06-02
申请号：US14083733
申请日：2013-11-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Heung-kyu Kwon , Seok-won Lee , Hyon-chol Kim , Su-chang Lee , Chi-young Lee
CPC classification number: H01L24/17 , H01L22/12 , H01L22/20 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/00 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
Abstract translation: 半导体封装可以包括具有第一表面和第二表面的衬底本体。 半导体芯片可以安装在第一表面上，并且多个电极焊盘可以在第二表面上并且选择性地形成为具有从基板主体的中心区域朝向基板主体的外边缘延伸的逐渐变小或更大的尺寸 在半导体封装的回流焊工艺翘曲曲线上。
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公开(公告)号：US10747250B2
公开(公告)日：2020-08-18
申请号：US16453149
申请日：2019-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok-won Lee , Nam-seog Kim
IPC: G05F1/575
Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.
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公开(公告)号：US09419011B2
公开(公告)日：2016-08-16
申请号：US14588506
申请日：2015-01-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunyeong Lee , Kyoung-Hoon Kim , Jin-Woo Park , SeungWoo Paek , Seok-won Lee , Taekeun Cho
IPC: H01L27/00 , H01L27/115
CPC classification number: H01L27/11582 , H01L27/11519 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L2224/32145
Abstract: Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an electrode structure and the electrode structure disposed under each cell pad. Insulating patterns of a mold stack structure for formation of the electrode structure may be supported by the plurality of dummy pillars, so transformation and contact of the insulating patterns may be minimized or prevented.
Abstract translation: 提供三维（3D）半导体器件。 3D半导体器件包括穿过电极结构的每个电池衬垫的多个虚拟柱和设置在每个电池衬垫下方的电极结构。 用于形成电极结构的模具堆叠结构的绝缘图案可以由多个虚拟支柱支撑，因此可以最小化或防止绝缘图案的变形和接触。
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公开(公告)号：US20200219834A1
公开(公告)日：2020-07-09
申请号：US16819851
申请日：2020-03-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-youn KIM , Seok-hyun Lee , Youn-ji Min , Kyoung-lim Suk , Seok-won Lee
IPC: H01L23/00 , H01L23/522 , H01L23/528 , H01L23/31 , H01L21/683 , H01L21/48 , H01L25/065 , H01L23/498
Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.
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