公开(公告)号：US08716872B2

公开(公告)日：2014-05-06

申请号：US13970071

申请日：2013-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-kyu Kwon ,  Su-chang Lee

IPC: H01L25/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract translation: 叠层半导体封装具有包括第一封装基板和安装在第一封装基板上的第一半导体芯片的第一半导体封装，第二半导体封装，包括第二封装基板和安装在第二封装基板上的第二半导体芯片，以及多个 的电连接第一和第二半导体封装的连接。 连接被布置在第一半导体芯片外部的第一封装基板的外部区域上。 连接沿着第一封装衬底的相对的第一长边和相对较短的第二侧布置。 沿着每个更长的第一侧布置的那些连接的高度从较长的第一侧的中心到外部区域（即，端部）逐渐变化。

公开(公告)号：US09048168B2

公开(公告)日：2015-06-02

申请号：US14083733

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/66 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/00 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract translation: 半导体封装可以包括具有第一表面和第二表面的衬底本体。 半导体芯片可以安装在第一表面上，并且多个电极焊盘可以在第二表面上并且选择性地形成为具有从基板主体的中心区域朝向基板主体的外边缘延伸的逐渐变小或更大的尺寸 在半导体封装的回流焊工艺翘曲曲线上。

公开(公告)号：US20130334708A1

公开(公告)日：2013-12-19

申请号：US13970071

申请日：2013-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-kyu Kwon ,  Su-chang Lee

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract translation: 叠层半导体封装具有包括第一封装基板和安装在第一封装基板上的第一半导体芯片的第一半导体封装，第二半导体封装，包括第二封装基板和安装在第二封装基板上的第二半导体芯片，以及多个 的电连接第一和第二半导体封装的连接。 连接被布置在第一半导体芯片外部的第一封装基板的外部区域上。 连接沿着第一封装衬底的相对的第一长边和相对较短的第二侧布置。 沿着每个更长的第一侧布置的那些连接的高度从较长的第一侧的中心到外部区域（即，端部）逐渐变化。

公开(公告)号：US09601458B2

公开(公告)日：2017-03-21

申请号：US14207732

申请日：2014-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heung-kyu Kwon ,  Su-chang Lee

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

公开(公告)号：US20140193951A1

公开(公告)日：2014-07-10

申请号：US14207732

申请日：2014-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heung-kyu Kwon ,  Su-chang Lee

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract translation: 叠层半导体封装具有包括第一封装基板和安装在第一封装基板上的第一半导体芯片的第一半导体封装，第二半导体封装，包括第二封装基板和安装在第二封装基板上的第二半导体芯片，以及多个 的电连接第一和第二半导体封装的连接。 连接被布置在第一半导体芯片外部的第一封装基板的外部区域上。 连接沿着第一封装衬底的相对的第一长边和相对较短的第二侧布置。 沿着每个更长的第一侧布置的那些连接的高度从较长的第一侧的中心到外部区域（即，端部）逐渐变化。

公开(公告)号：US20140077382A1

公开(公告)日：2014-03-20

申请号：US14083733

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/00 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract translation: 半导体封装可以包括具有第一表面和第二表面的衬底本体。 半导体芯片可以安装在第一表面上，并且多个电极焊盘可以在第二表面上并且选择性地形成为具有从基板主体的中心区域朝向基板主体的外边缘延伸的逐渐变小或更大的尺寸 在半导体封装的回流焊工艺翘曲曲线上。