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1.发明授权Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same 有权非易失性存储器件包括外围电路，以接收与信号的上升沿和下降沿中的一个同步的地址，而不管是选择第一还是第二对准类型，并且包括其的非易失性存储器系统公开(公告)号：US09368168B2
公开(公告)日：2016-06-14
申请号：US14856218
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。
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公开(公告)号：USD730910S1
公开(公告)日：2015-06-02
申请号：US29507456
申请日：2014-10-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer： Gwang-Man Lim , Il-Mok Kang , Seok-Jae Han , Sang-Chul Kang , Seok-Cheon Kwon , Seok-Chan Lee
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公开(公告)号：USD736776S1
公开(公告)日：2015-08-18
申请号：US29507467
申请日：2014-10-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer： Gwang-Man Lim , Il-Mok Kang , Seok-Jae Han , Sang-Chul Kang , Seok-Cheon Kwon , Seok-Chan Lee
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公开(公告)号：US09817434B2
公开(公告)日：2017-11-14
申请号：US14989575
申请日：2016-01-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bo-Geun Kim , Kye-Hyun Kyung , Jae-Yong Jeong , Seung-Hun Choi , Seok-Cheon Kwon , Chul-Ho Lee
IPC: G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F1/14 , G06F1/32 , G06F13/16 , G06F1/04 , G11C7/22 , G06F3/06
CPC classification number: G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
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公开(公告)号：US20160005484A1
公开(公告)日：2016-01-07
申请号：US14856261
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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Patent Agency Ranking
公开(公告)号：US20160005482A1
公开(公告)日：2016-01-07
申请号：US14856182
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KYEONG-HAN LEE , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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公开(公告)号：US09691015B2
公开(公告)日：2017-06-27
申请号：US15157507
申请日：2016-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok-Cheon Kwon , Jae-Bum Lee , Seok-Heon Lee
IPC: G06K19/06 , G06K19/077
CPC classification number: G06K19/07732 , G06K19/07741
Abstract: Memory card adapters and/or a memory apparatuses may be provided. For example, a memory card adapter including a main housing section that corresponds to a memory card socket of a first standard, the main housing section including a card housing section, the card housing section configured to house a memory card of a second standard different from the first standard therein, a first surface of the main housing section defining a through-hole, the through-hole configured to expose a connection pin of the memory card to be housed in the housing section to an outside of the housing section, and a second surface of the main housing section defining a card insertion hole, the second surface being different from the first surface, the card insertion hole configured to receive the memory card into the card housing section may be provided.
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公开(公告)号：USD736775S1
公开(公告)日：2015-08-18
申请号：US29507078
申请日：2014-10-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer： Gwang-Man Lim , Il-Mok Kang , Seok-Jae Han , Sang-Chul Kang , Seok-Cheon Kwon , Seok-Chan Lee
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公开(公告)号：USD730911S1
公开(公告)日：2015-06-02
申请号：US29507479
申请日：2014-10-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer： Gwang-Man Lim , Il-Mok Kang , Seok-Jae Han , Sang-Chul Kang , Seok-Cheon Kwon , Seok-Chan Lee
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公开(公告)号：USD730908S1
公开(公告)日：2015-06-02
申请号：US29507097
申请日：2014-10-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer： Gwang-Man Lim , Il-Mok Kang , Seok-Jae Han , Sang-Chul Kang , Seok-Cheon Kwon , Seok-Chan Lee
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