公开(公告)号：US20220208293A1

公开(公告)日：2022-06-30

申请号：US17374822

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

公开(公告)号：US20210208965A1

公开(公告)日：2021-07-08

申请号：US16860241

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanguhn CHA ,  Juseong HWANG

IPC: G06F11/10 ,  G06F11/07 ,  G11C11/406

Abstract: A semiconductor memory device includes an ECC circuit; an error information register; a scrubbing control circuit to count refresh row addresses and output a scrubbing address for a scrubbing operation to be performed on at least one sub-page in a first memory cell row each time N refresh row addresses are counted; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword; and record the error information in the error information register and selectively determine, based on the error information, whether to write back a corrected first codeword in a memory location in which the data corresponding to the first codeword is stored.

公开(公告)号：US20250029672A1

公开(公告)日：2025-01-23

申请号：US18904922

申请日：2024-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20210311820A1

公开(公告)日：2021-10-07

申请号：US17351619

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn CHA ,  Hoyoung SONG ,  Myungkyu LEE ,  Sunghye CHO

IPC: G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US20210193245A1

公开(公告)日：2021-06-24

申请号：US16864787

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

公开(公告)号：US20240201868A1

公开(公告)日：2024-06-20

申请号：US18588599

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20230223095A1

公开(公告)日：2023-07-13

申请号：US18113702

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/4401 ,  G11C2029/1204

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

公开(公告)号：US20210311821A1

公开(公告)日：2021-10-07

申请号：US17088900

申请日：2020-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Namsung KIM ,  Sanguhn CHA ,  Jaeyoun Youn ,  Kijun Lee

IPC: G06F11/10 ,  H01L25/065

Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

公开(公告)号：US20160350181A1

公开(公告)日：2016-12-01

申请号：US15156804

申请日：2016-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn CHA ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

IPC: G06F11/10 ,  H03M13/15 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  H03M13/1575

Abstract: A semiconductor memory device capable of detecting a miscorrected bit generated in the semiconductor memory device outside the semiconductor memory device and a memory system including the semiconductor memory device are disclosed. The semiconductor memory device may generate first check bits based on first data received from the outside, divide an error correcting code (ECC) code word including the first data and the first check bits into a plurality of code word groups, and dispose a miscorrected bit, caused by error bits included in a first ECC code word group, in another ECC code word group rather than the first ECC code word group.

Abstract translation: 公开了一种半导体存储器件，其能够检测在半导体存储器件外部的半导体存储器件中产生的错误校正位和包括该半导体存储器件的存储器系统。 半导体存储器件可以基于从外部接收的第一数据生成第一校验位，将包括第一数据和第一校验位的纠错码（ECC）码字分成多个码字组，并且配置未校正位 由包含在第一ECC码字组中的错误位引起的，在另一ECC码字组而不是第一ECC码字组中引起的。