公开(公告)号：US20220122685A1

公开(公告)日：2022-04-21

申请号：US17313236

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggi AHN ,  Yesin RYU ,  Jun Jin KONG ,  Eunae LEE ,  Jihyun CHOI

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/14 ,  G11C29/52

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

公开(公告)号：US20220197739A1

公开(公告)日：2022-06-23

申请号：US17388243

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sunggi Ahn ,  Jaeyoun Youn

IPC: G06F11/10

Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.

公开(公告)号：US20210193245A1

公开(公告)日：2021-06-24

申请号：US16864787

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

公开(公告)号：US20240095122A1

公开(公告)日：2024-03-21

申请号：US18513730

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sunggi AHN ,  Jaeyoun YOUN

IPC: G06F11/10

CPC classification number: G06F11/106

Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.

公开(公告)号：US20230144712A1

公开(公告)日：2023-05-11

申请号：US18096053

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sunggi AHN ,  Jaeyoun YOUN

IPC: G06F11/10

CPC classification number: G06F11/106

Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.

公开(公告)号：US20200319960A1

公开(公告)日：2020-10-08

申请号：US16668090

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn Cha ,  Hyungi Kim ,  Hoon Shin

IPC: G06F11/10 ,  G11C29/42

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.