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公开(公告)号：US20220208293A1
公开(公告)日：2022-06-30
申请号：US17374822
申请日：2021-07-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiheung KIM , Sanguhn CHA , Junhyung KIM , Sungchul PARK , Hyojin JUNG , Kyungsoo HA
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
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Patent Agency Ranking
2.发明申请METHOD OF OPERATING INTEGRATED MESSAGE APPLICATION AND ELECTRONIC DEVICE SUPPORTING SAME 有权一体化消息应用程序的运行方法及其支持的电子设备公开(公告)号：US20160227019A1
公开(公告)日：2016-08-04
申请号：US15000122
申请日：2016-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keehwan SEOL , Yongseok PARK , Hyojin JUNG
CPC classification number: H04M1/72552 , H04L51/16 , H04L51/36 , H04W4/12
Abstract: A method comprising: selecting, by an electronic device, a conversation partner; identifying, by the electronic device, one or more message types that are associated with the conversation partner; generating, by the electronic device, a set of one or more tabs corresponding to the message types; and displaying the set of one or more tabs in a user interface for exchanging communications with the conversation partner.
Abstract translation: 一种方法，包括：通过电子设备选择对话伙伴; 通过电子设备识别与对话伙伴相关联的一个或多个消息类型; 由所述电子设备生成与所述消息类型对应的一组或多个选项卡; 以及在用户界面中显示一个或多个标签的集合，以与对话伙伴交换通信。
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公开(公告)号：US20250029672A1
公开(公告)日：2025-01-23
申请号：US18904922
申请日：2024-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiheung KIM , Sanguhn CHA , Junhyung KIM , Sungchul PARK , Hyojin JUNG , Kyungsoo HA
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
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公开(公告)号：US20190287331A1
公开(公告)日：2019-09-19
申请号：US16355402
申请日：2019-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghyuk LEE , Yongseok PARK , Hyojin JUNG
Abstract: An electronic apparatus and an operating method thereof according to various embodiments may: transmit reference information, detected from a first external device, to a second external device; receive first password information, generated on the basis of the reference information, from the second external device; and provide the first password information to the first external device so that the first external device controls a locking device on the basis of the first password information.
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公开(公告)号：US20230223095A1
公开(公告)日：2023-07-13
申请号：US18113702
申请日：2023-02-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiheung KIM , Sanguhn CHA , Junhyung KIM , Sungchul PARK , Hyojin JUNG , Kyungsoo HA
CPC classification number: G11C29/42 , G11C29/20 , G11C29/4401 , G11C2029/1204
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
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公开(公告)号：US20220208252A1
公开(公告)日：2022-06-30
申请号：US17400585
申请日：2021-08-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiheung KIM , Junhyung KIM , Sungchul PARK , Hangyun JUNG , Hyojin JUNG , Kyungsoo HA
IPC: G11C11/4091 , G11C11/402 , G06F7/58 , G11C11/408
Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.
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