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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220208293A1

    公开(公告)日：2022-06-30

    申请号：US17374822

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20250029672A1

    公开(公告)日：2025-01-23

    申请号：US18904922

    申请日：2024-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C29/42 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220208252A1

    公开(公告)日：2022-06-30

    申请号：US17400585

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiheung KIM ,  Junhyung KIM ,  Sungchul PARK ,  Hangyun JUNG ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C11/4091 ,  G11C11/402 ,  G06F7/58 ,  G11C11/408

    Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

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