知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20250029672A1

    公开(公告)日：2025-01-23

    申请号：US18904922

    申请日：2024-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C29/42 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220208252A1

    公开(公告)日：2022-06-30

    申请号：US17400585

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiheung KIM ,  Junhyung KIM ,  Sungchul PARK ,  Hangyun JUNG ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C11/4091 ,  G11C11/402 ,  G06F7/58 ,  G11C11/408

    Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240203475A1

    公开(公告)日：2024-06-20

    申请号：US18593937

    申请日：2024-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230021622A1

    公开(公告)日：2023-01-26

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H03M13/11 ,  H03M13/00

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220208293A1

    公开(公告)日：2022-06-30

    申请号：US17374822

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung KIM ,  Sanguhn CHA ,  Junhyung KIM ,  Sungchul PARK ,  Hyojin JUNG ,  Kyungsoo HA

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

Patent Agency Ranking