METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PERFORMING THE SAME

    公开(公告)号:US20230187011A1

    公开(公告)日:2023-06-15

    申请号:US17854638

    申请日:2022-06-30

    IPC分类号: G11C29/52 G11C29/02

    摘要: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.

    STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

    公开(公告)号:US20210202012A1

    公开(公告)日:2021-07-01

    申请号:US16990262

    申请日:2020-08-11

    摘要: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

    NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD USING HARD AND SOFT DECISION DECODING
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD USING HARD AND SOFT DECISION DECODING 有权
    非易失性存储器件和使用硬和软决策解码的相关读取方法

    公开(公告)号:US20130326314A1

    公开(公告)日:2013-12-05

    申请号:US13786509

    申请日:2013-03-06

    IPC分类号: H03M13/37

    摘要: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

    摘要翻译: 存储装置包括包括多个存储器单元的非易失性存储器件,以及错误校正电路,被配置为从非易失性存储器件接收主数据和辅助数据,并对主数据进行硬判决解码操作,并进一步被配置为执行 基于次要数据对主数据进行软判决解码操作。 在硬判决读取操作中从多个存储器单元中读取主数据,并且从主数据中从被编程到特定状态的存储器单元读取次数据。

    HOMOMORPHIC ENCRYPTION OPERATOR, STORAGE DEVICE INCLUDING THE SAME, AND LEVEL CONFIGURATION METHOD THEREOF

    公开(公告)号:US20240072992A1

    公开(公告)日:2024-02-29

    申请号:US18312936

    申请日:2023-05-05

    IPC分类号: H04L9/00 H04L9/08

    CPC分类号: H04L9/008 H04L9/0869

    摘要: A homomorphic encryption operator includes: a level configuration unit configured to set an encryption level by selecting a plurality of prime numbers of different values according to a scale factor condition used for multiplication of a homomorphic encryption operation and an increase/decrease condition for increasing or decreasing consecutively selected prime numbers, and a modular multiplication operator configured to perform lightweight modular multiplication using the selected plurality of prime numbers, wherein the level configuration unit includes: a level constructor configured to select prime number sets whose number have selected Hamming weights, respectively, based on the scale factor condition and the increase/decrease condition, and wherein the level configuration unit is further configured to configure the selected prime number sets with the encryption level using a prime number table.

    NONVOLATILE MEMORY DEVICE AND ERROR CORRECTION METHODS THEREOF
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND ERROR CORRECTION METHODS THEREOF 有权
    非易失性存储器件及其错误校正方法

    公开(公告)号:US20130326296A1

    公开(公告)日:2013-12-05

    申请号:US13788592

    申请日:2013-03-07

    IPC分类号: G11C29/50

    摘要: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.

    摘要翻译: 提供了一种用于处理从非易失性存储器读取的数据的数据处理方法。 数据处理方法包括在存储器控制器处从非易失性存储器接收第一位数据,并且基于存储在存储器控制器中的第一位数据和第二位数据执行擦除解码。 第一位数据指示擦除的存储单元,并且在先前纠错解码期间使用读取电压读取第二位数据。