公开(公告)号：US20230040733A1

公开(公告)日：2023-02-09

申请号：US17846606

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu YU ,  Woojin RIM ,  Jungho DO ,  Jaewoo SEO ,  Hyeongyu YOU ,  Minjae JEONG

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

Abstract: Provided is an integrated circuit including standard cells arranged over a plurality of rows. The standard cells may include: a plurality of functional cells each implemented as a logic circuit; and a plurality of filler cells including at least one first filler cell and at least one second filler cell that each include at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell.

公开(公告)号：US20240128159A1

公开(公告)日：2024-04-18

申请号：US18367549

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jaehee CHO ,  Geonwoo NAM ,  Jungho DO ,  Jisu YU ,  Hyeongyu YOU ,  Seungyoung LEE

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit including a standard cell including: a metal layer including a pattern extending in a first horizontal direction and a plurality of tracks spaced apart from one another in a second horizontal direction, wherein the plurality of tracks include a plurality of cell tracks and one power distribution network (PDN) track, wherein cell patterns are formed on the plurality of cell tracks, and a PDN pattern or a routing pattern is formed on the one power distribution network (PDN) track, wherein a first pattern is spaced apart from a cell boundary of the standard cell by a first length and is formed on a first cell track among the plurality of cell tracks, and wherein a second pattern is spaced apart from a cell boundary of the standard cell by a second length and is formed on a second cell track among the plurality of cell tracks.

公开(公告)号：US20230142050A1

公开(公告)日：2023-05-11

申请号：US17984417

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongyu YOU ,  Jungho DO ,  Sangdo PARK ,  Jaewoo SEO ,  Jisu YU ,  Minjae JEONG ,  Dayeon CHO

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/06 ,  H01L28/88 ,  H01L27/0207

Abstract: An integrated circuit including a plurality of stacked metal layers and a method of manufacturing the integrated circuit are provided. The method includes: providing a plurality of standard cells, each of which includes cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.

公开(公告)号：US20250151350A1

公开(公告)日：2025-05-08

申请号：US18940454

申请日：2024-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu YOU ,  Jaewoo SEO ,  Geonwoo NAM ,  Minjae JEONG ,  Jaehee CHO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit may include: a plurality of wells extending in parallel with each other in a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; a plurality of first doped regions disposed on the plurality of wells in a first region and a second region, the first region being separated from the second region in the first direction, the plurality of first doped regions having the first conductivity type; a plurality of second doped regions disposed on the substrate between the plurality of wells in the first region and the second region and having the second conductivity type; and a plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having the first conductivity type.

公开(公告)号：US20220375962A1

公开(公告)日：2022-11-24

申请号：US17576279

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjae JEONG ,  JUNGHO DO ,  JAE-WOO SEO ,  JISU YU ,  HYEONGYU YOU

IPC: H01L27/118 ,  H01L27/02 ,  H01L21/768 ,  G03F1/36 ,  G06F30/398

Abstract: A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

公开(公告)号：US20220300693A1

公开(公告)日：2022-09-22

申请号：US17669631

申请日：2022-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Jaewoo SEO ,  Sanghoon BAEK ,  Jisu YU ,  Hyeongyu YOU ,  Minjae JEONG

IPC: G06F30/394 ,  G06F30/392

Abstract: An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.

公开(公告)号：US20240055431A1

公开(公告)日：2024-02-15

申请号：US18222734

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jisu YU ,  Geonwoo NAM ,  Jungho DO ,  Hyeongyu YOU ,  Jaehee CHO

IPC: H01L27/092 ,  H01L23/528 ,  G06F30/392

CPC classification number: H01L27/0922 ,  H01L23/528 ,  G06F30/392

Abstract: An integrated circuit includes a first cell disposed in a first row and a second row, which are adjacent to each other and extend in a first direction, and including a plurality of first threshold voltage devices and at least one second cell disposed adjacent to the first cell in at least one of the first row and the second row and including at least one second threshold voltage device, wherein the plurality of first threshold voltage devices include at least one first device configured to perform a first function in the first row and at least one second device configured to perform a second function, which is different from the first function, in the second row.

公开(公告)号：US20220262785A1

公开(公告)日：2022-08-18

申请号：US17540345

申请日：2021-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu YU ,  Jaewoo SEO ,  Hyeongyu YOU ,  Minjae JEONG

IPC: H01L27/02 ,  H01L23/528 ,  G06F30/392

Abstract: An integrated circuit (IC) includes: a plurality of gate electrodes extending in a first direction and arranged in a second direction that is orthogonal to the first direction; a plurality of first power lines extending in the first direction to supply power to the standard cell, and respectively placed to be adjacent to first sides of the gate electrodes; and a plurality of signal lines extending in the first direction to transfer an input signal or an output signal of the standard cell, and respectively placed to be adjacent to second sides of the gate electrodes.