公开(公告)号：US20240055431A1

公开(公告)日：2024-02-15

申请号：US18222734

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jisu YU ,  Geonwoo NAM ,  Jungho DO ,  Hyeongyu YOU ,  Jaehee CHO

IPC: H01L27/092 ,  H01L23/528 ,  G06F30/392

CPC classification number: H01L27/0922 ,  H01L23/528 ,  G06F30/392

Abstract: An integrated circuit includes a first cell disposed in a first row and a second row, which are adjacent to each other and extend in a first direction, and including a plurality of first threshold voltage devices and at least one second cell disposed adjacent to the first cell in at least one of the first row and the second row and including at least one second threshold voltage device, wherein the plurality of first threshold voltage devices include at least one first device configured to perform a first function in the first row and at least one second device configured to perform a second function, which is different from the first function, in the second row.

公开(公告)号：US20250151350A1

公开(公告)日：2025-05-08

申请号：US18940454

申请日：2024-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu YOU ,  Jaewoo SEO ,  Geonwoo NAM ,  Minjae JEONG ,  Jaehee CHO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit may include: a plurality of wells extending in parallel with each other in a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; a plurality of first doped regions disposed on the plurality of wells in a first region and a second region, the first region being separated from the second region in the first direction, the plurality of first doped regions having the first conductivity type; a plurality of second doped regions disposed on the substrate between the plurality of wells in the first region and the second region and having the second conductivity type; and a plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having the first conductivity type.

公开(公告)号：US20240128159A1

公开(公告)日：2024-04-18

申请号：US18367549

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jaehee CHO ,  Geonwoo NAM ,  Jungho DO ,  Jisu YU ,  Hyeongyu YOU ,  Seungyoung LEE

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit including a standard cell including: a metal layer including a pattern extending in a first horizontal direction and a plurality of tracks spaced apart from one another in a second horizontal direction, wherein the plurality of tracks include a plurality of cell tracks and one power distribution network (PDN) track, wherein cell patterns are formed on the plurality of cell tracks, and a PDN pattern or a routing pattern is formed on the one power distribution network (PDN) track, wherein a first pattern is spaced apart from a cell boundary of the standard cell by a first length and is formed on a first cell track among the plurality of cell tracks, and wherein a second pattern is spaced apart from a cell boundary of the standard cell by a second length and is formed on a second cell track among the plurality of cell tracks.