公开(公告)号：US20220020691A1

公开(公告)日：2022-01-20

申请号：US17180491

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONGYU YOU ,  JISU YU ,  JAE-WOO SEO ,  SEUNG MAN LIM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

公开(公告)号：US20220375962A1

公开(公告)日：2022-11-24

申请号：US17576279

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjae JEONG ,  JUNGHO DO ,  JAE-WOO SEO ,  JISU YU ,  HYEONGYU YOU

IPC: H01L27/118 ,  H01L27/02 ,  H01L21/768 ,  G03F1/36 ,  G06F30/398

Abstract: A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.