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    SEMICONDUCTOR DEVICE WITH MEMORY STRING
    1.
    发明申请
    SEMICONDUCTOR DEVICE WITH MEMORY STRING 有权

    公开(公告)号：US20250140316A1

    公开(公告)日：2025-05-01

    申请号：US18909041

    申请日：2024-10-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwangsoo Kim

    IPC: G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

    Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, the cell structure including gate electrodes spaced apart from each other in a vertical direction, a channel structure arranged within a channel hole extending in the vertical direction by passing through the gate electrodes, including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion, a common source layer connected to the channel layer at the second end portion of the channel structure, an upper insulating layer on the common source layer, and a back gate contact arranged within a first backside contact hole passing through the upper insulating layer and the common source layer and connected to the back gate electrode.

    Vertical memory devices
    4.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11158651B2

    公开(公告)日：2021-10-26

    申请号：US16773103

    申请日：2020-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Kwangsoo Kim ,  Taehun Kim ,  Yongseok Kim ,  Kohji Kanamori

    IPC: H01L29/792 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02

    Abstract: A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.

    CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    8.
    发明申请
    CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20250158001A1

    公开(公告)日：2025-05-15

    申请号：US18780621

    申请日：2024-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Chiwoo Lee

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

    Abstract: A chip structure including a semiconductor chip, a photonic integrated circuit chip spaced apart from the semiconductor chip in a horizontal direction, an electronic integrated circuit chip on the semiconductor chip and the photonic integrated circuit chip, a first molding layer surrounding the semiconductor chip and the photonic integrated circuit chip, and a second molding layer on the semiconductor chip, the photonic integrated circuit chip, and the first molding layer and surrounding the electronic integrated circuit chip. A portion of the electronic integrated circuit chip overlaps the photonic integrated circuit chip in a vertical direction, and another portion of the electronic integrated circuit chip overlaps the semiconductor chip in the vertical direction.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250062237A1

    公开(公告)日：2025-02-20

    申请号：US18648683

    申请日：2024-04-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwangsoo Kim ,  Hyunsoo Chung ,  Jungul Hwang

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

    Abstract: Provided is a semiconductor package including a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a circuit board disposed between the first redistribution layer and the first semiconductor chip, bonding wires connecting the first semiconductor chip and the circuit board to each other, a second redistribution layer disposed on the first semiconductor chip, a second semiconductor chip disposed on the second redistribution layer, and conductive posts connecting the first redistribution layer and the second redistribution layer to each other.

    NON-VOLATILE MEMORY DEVICE AND A METHOD OF OPERATING THE SAME
    10.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND A METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20250095759A1

    公开(公告)日：2025-03-20

    申请号：US18796585

    申请日：2024-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ilho Myeong ,  Kwangsoo Kim ,  Suseong Noh

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32

    Abstract: A method of operating a memory device, the method including: applying a program inhibition voltage to an unselected bit line in a first program loop of a plurality of program loops; applying a program permission voltage to a selected bit line in the first program loop; applying a pass voltage to an unselected word line in the first program loop; applying a program voltage to a selected word line in the first program loop; applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line, in the first program loop; and applying a verification voltage to the selected word line after applying the pulse voltage to the selected word line, in the first program loop.

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