公开(公告)号：US20180102260A1

公开(公告)日：2018-04-12

申请号：US15700491

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Hye HWANG ,  Youn-Joung CHO ,  Won-Woong CHUNG ,  Nam-Gun KIM ,  Kong-Soo LEE ,  Badro IM ,  Yoon-Chul CHO

IPC: H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32139 ,  C23C16/0272 ,  C23C16/04 ,  C23C16/24 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32055 ,  H01L27/10885

Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.

公开(公告)号：US20130175491A1

公开(公告)日：2013-07-11

申请号：US13729742

申请日：2012-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jong HAN ,  Kong-Soo LEE ,  Yoon-Goo KANG ,  Ho-Kyun AN ,  Seong-Hoon JEONG

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract translation: 半导体器件及其制造方法包括半导体衬底中的场区以限定有源区。 层间绝缘层位于半导体衬底上。 半导体图案在垂直延伸穿过层间绝缘层的孔内。 半导体图案与有源区域接触。 阻挡区域在半导体图案和层间绝缘层之间。 阻挡区域包括第一缓冲介电材料和阻挡介电材料。 第一缓冲电介质材料在阻挡介电材料和半导体图案之间，并且阻挡介电材料与半导体图案和有源区两者间隔开。

公开(公告)号：US20230137072A1

公开(公告)日：2023-05-04

申请号：US17849086

申请日：2022-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon KIM ,  Yurim KIM ,  Seohee PARK ,  Kong-Soo LEE ,  Yong Suk TAK

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/78

Abstract: A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.

公开(公告)号：US20230134099A1

公开(公告)日：2023-05-04

申请号：US17825441

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon KIM ,  Yurim KIM ,  Seohee PARK ,  Kong-Soo LEE ,  Yong Suk TAK

IPC: H01L27/108

Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

公开(公告)号：US20170062435A1

公开(公告)日：2017-03-02

申请号：US15162912

申请日：2016-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hyun IM ,  Han-Jin LIM ,  Jin-Won MA ,  Kong-Soo LEE ,  Ki-Vin IM

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L27/10814 ,  B82Y10/00 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L23/535 ,  H01L27/10823 ,  H01L27/10852 ,  H01L28/90 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/775

Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.

Abstract translation: 提供半导体器件及其制造方法。 半导体装置可以包括基板，基板上的金属层，金属层上的种子层，种子层上的柱状的纳米线，保形地覆盖纳米线的电介质膜，以及电介质膜上的电极膜 。