BIT LINE SENSE AMPLIFIER AND BIT LINE SENSING METHOD OF SEMICONDUCTOR MEMORY DEVICE

    公开(公告)号:US20230395102A1

    公开(公告)日:2023-12-07

    申请号:US18205057

    申请日:2023-06-02

    CPC classification number: G11C7/08 G11C7/12 G11C7/109

    Abstract: A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.

Patent Agency Ranking