公开(公告)号：US20160351408A1

公开(公告)日：2016-12-01

申请号：US15130515

申请日：2016-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BADRO IM ,  YOONCHUL CHO ,  SANGYEOL KANG ,  DAEHYUN KIM ,  DONGKAK LEE ,  JUN-NOH LEE ,  BONGHYUN KIM ,  KONGSOO LEE

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/0337 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32139

Abstract: Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.

Abstract translation: 在蚀刻目标层上形成含碳图案，通过亲水处理处理含碳图案的侧表面，亲水处理已经在含碳图案的侧表面上形成多晶硅间隔物 并且使用多晶硅间隔物作为蚀刻掩模来图案化蚀刻目标层。

公开(公告)号：US20140120685A1

公开(公告)日：2014-05-01

申请号：US13791870

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Hoon JEONG ,  Yoongoo KANG ,  Ho-Kyun AN ,  KONGSOO LEE ,  JAEJONG HAN

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device and method of forming a semiconductor device is disclosed. The method includes forming a first ion-implanted layer having an amorphous state in a substrate; forming an impurity region of a first conductive type in the substrate; forming a semiconductor pattern on the substrate; forming a first doped region of the first conductive type in the semiconductor pattern; and forming a second doped region of a second conductive type contrary to the first conductive type in the semiconductor pattern. The first ion-implanted layer is formed by implanting carbons ions or germanium ions in the substrate.

Abstract translation: 公开了一种形成半导体器件的半导体器件和方法。 该方法包括在基板中形成具有非晶状态的第一离子注入层; 在衬底中形成第一导电类型的杂质区; 在所述基板上形成半导体图案; 在半导体图案中形成第一导电类型的第一掺杂区域; 以及形成与所述半导体图案中的所述第一导电类型相反的第二导电类型的第二掺杂区域。 第一离子注入层通过在基底中注入碳离子或锗离子而形成。

公开(公告)号：US20190148383A1

公开(公告)日：2019-05-16

申请号：US16245307

申请日：2019-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  JUN-NOH LEE ,  DONG-HYUN IM ,  YOUNGSEOK KIM ,  KONGSOO LEE

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20240003007A1

公开(公告)日：2024-01-04

申请号：US18138192

申请日：2023-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PYUNG MOON ,  KIHYUN KIM ,  HYOUNGSUB KIM ,  HOIJOON KIM ,  GEUNYOUNG YEOM ,  KONGSOO LEE ,  HEESOO LEE

IPC: C23C16/455 ,  H01J37/32 ,  H01L29/16 ,  H01L29/51

CPC classification number: C23C16/45536 ,  H01L29/517 ,  H01L29/1606 ,  H01J37/32357

Abstract: A method of manufacturing an integrated circuit device includes alternately stacking sacrificial semiconductor layers and channel layers on a substrate to form a stack structure, forming source regions and drain regions on both sides of the stack structure, forming a gate space between the channel layers by removing the sacrificial semiconductor layers, forming the channel layers to be spaced apart from each other in a perpendicular direction to the substrate, performing a plasma treatment of boron trichloride (BCL3) on the channel layers, forming gate dielectric layers on the channel layers on which the plasma treatment of boron trichloride (BCL3) is performed, and forming gate layers covering the gate dielectric layers in the gate space.