公开(公告)号：US20210210342A1

公开(公告)日：2021-07-08

申请号：US16925532

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNYEONG LEE ,  MINKYU PARK ,  INSUN YI ,  BEOMSEOK KIM ,  YOUNGSEOK KIM ,  KUNTACK LEE

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/108 ,  H01L27/115 ,  H01J37/32 ,  C23C16/511 ,  C23C16/46 ,  C23C16/40

Abstract: A thin film formation apparatus includes a chamber, a platen disposed within the chamber, a heater configured to heat the platen within the chamber, a gas inlet communicating with an interior of the chamber and configured to supply a reducing gas and inert gas to the interior of the chamber, a target disposed within the chamber and spatially separated from the platen, and a microwave plasma source disposed adjacent to the target. The reducing gas includes at least one of hydrogen (H2) and deuterium (D2)

公开(公告)号：US20190148383A1

公开(公告)日：2019-05-16

申请号：US16245307

申请日：2019-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  JUN-NOH LEE ,  DONG-HYUN IM ,  YOUNGSEOK KIM ,  KONGSOO LEE

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20170329888A1

公开(公告)日：2017-11-16

申请号：US15433835

申请日：2017-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGSEOK KIM ,  NOYOUNG CHUNG

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A method for manufacturing a semiconductor device includes obtaining a design layout for a target layer of an optical proximity correction process, the design layout including a first block and a second block being a repetition block of the first block, dividing the design layout into a plurality of patches, performing the optical proximity correction process on the patches of the first block, applying corrected patches of the first block to the patches of the second block, respectively, forming a correction layout by performing the optical proximity correction process on boundary patches of the second block, fabricating a photomask corresponding to the correction layout, and forming patterns on a substrate corresponding to the photomask. Each of the patches is a standard unit on which the optical proximity correction process is performed.