公开(公告)号：US20230154866A1

公开(公告)日：2023-05-18

申请号：US17875639

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Juyoun CHOI ,  Miyeon KIM ,  Jungil SON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/14 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2224/14517 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.

公开(公告)号：US20240071882A1

公开(公告)日：2024-02-29

申请号：US18366098

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongho SHIN ,  Sangkyu KIM ,  Juyoun CHOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32146 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A semiconductor package may include a package substrate and a silicon-free interposer. The silicon-free interposer may include a second core layer, first interposer through electrodes passing through the second core layer and connected to the first core through electrodes, and second interposer through electrodes passing through the second core layer and connected to the second core through electrodes. Diameters of the first core through electrodes may be different from diameters of the second core through electrodes, and diameters of the first interposer through electrodes may be different from diameters of the second interposer through electrodes.

公开(公告)号：US20230317640A1

公开(公告)日：2023-10-05

申请号：US18075878

申请日：2022-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun CHOI ,  Seongho SHIN

IPC: H01L23/64 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/64 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package is provided. The semiconductor package includes: a lower equipotential plate provided in a lower wiring layer; an upper equipotential plate provided in an upper wiring layer; a pair of differential signal wiring lines provided in a signal wiring layer that is between the lower equipotential plate and the upper equipotential plate, wherein the pair of differential signal wiring lines includes a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other and extend in parallel; and a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer, the lower wiring layer, and the upper wiring layer. The wiring insulating layer includes a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer, and the first wiring insulating layer and the second wiring insulating layer include different materials.

公开(公告)号：US20230039914A1

公开(公告)日：2023-02-09

申请号：US17742862

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun CHOI ,  Eunjung LEE ,  Junho LEE ,  Seungsoo HA

IPC: H01L23/66 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.