公开(公告)号：US20240274510A1

公开(公告)日：2024-08-15

申请号：US18646015

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho DO ,  Seungyoung LEE

IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L27/0207 ,  H01L27/088

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

公开(公告)号：US20210104550A1

公开(公告)日：2021-04-08

申请号：US16941042

申请日：2020-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho DO

IPC: H01L27/118

Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

公开(公告)号：US20230178558A1

公开(公告)日：2023-06-08

申请号：US18155386

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho DO

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11881 ,  H01L2027/11875 ,  H01L2027/11851

Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

公开(公告)号：US20230004705A1

公开(公告)日：2023-01-05

申请号：US17941264

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho DO ,  Seung Hyun SONG

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  H01L29/78 ,  H01L27/092 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L27/11556

Abstract: A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.

公开(公告)号：US20210111257A1

公开(公告)日：2021-04-15

申请号：US16883308

申请日：2020-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan JUN ,  Jung Ho DO

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092

Abstract: Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.

公开(公告)号：US20200295134A1

公开(公告)日：2020-09-17

申请号：US16711582

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho DO ,  Rwik SENGUPTA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.