公开(公告)号：US20230178169A1

公开(公告)日：2023-06-08

申请号：US18062843

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpil SON

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G11C29/18 ,  G11C29/785

Abstract: A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.

公开(公告)号：US20220036958A1

公开(公告)日：2022-02-03

申请号：US17199955

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpil SON

IPC: G11C29/12 ,  G11C29/36 ,  G11C29/10

Abstract: A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop.

公开(公告)号：US20180204843A1

公开(公告)日：2018-07-19

申请号：US15699031

申请日：2017-09-08

Applicant: Samsung Electronics Co, Ltd.

Inventor： Jongpil SON

IPC: H01L27/112 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C17/16

Abstract: A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.

公开(公告)号：US20170213312A1

公开(公告)日：2017-07-27

申请号：US15407980

申请日：2017-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangoak WOO ,  Jongpil SON ,  Seungcheol BAEK ,  Soojung RYU

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.

公开(公告)号：US20170199697A1

公开(公告)日：2017-07-13

申请号：US15400103

申请日：2017-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minyoung SON ,  Jongpil SON ,  Minkyu JEONG

IPC: G06F3/06 ,  G09G5/39

CPC classification number: G06F3/0635 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0683 ,  G06F13/1673 ,  G06T1/60 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2352/00 ,  G09G2360/122 ,  G09G2360/18

Abstract: A memory apparatus including multiple buffers includes a memory controller configured to obtain memory allocation information based on a multi-write operation command, and a memory configured to store same graphics data in each of multiple buffers in a memory based on the memory allocation information.

公开(公告)号：US20170186213A1

公开(公告)日：2017-06-29

申请号：US15388520

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyu JEONG ,  Jongpil SON ,  Kwontaek KWON ,  Minyoung SON

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/04

Abstract: A method of determining a layout of textures includes acquiring a pattern of using textures when pixel shading is performed, based on shader codes, determining a layout of the textures based on the acquired pattern, and storing the textures in a memory according to the determined layout. Also provided is a corresponding apparatus.

公开(公告)号：US20240212776A1

公开(公告)日：2024-06-27

申请号：US18364303

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongpil SON

IPC: G11C29/12 ,  G11C29/14 ,  G11C29/42 ,  G11C29/46

CPC classification number: G11C29/1201 ,  G11C29/14 ,  G11C29/42 ,  G11C29/46

Abstract: A memory system includes a plurality of stacked memory dies. Each of the plurality of memory dies includes a first memory device connected to a first channel and a second memory device connected to a second channel. In a mirroring mode, when the first memory device performs a first write operation on write data, the second memory device performs a second write operation on the write data.

公开(公告)号：US20220328117A1

公开(公告)日：2022-10-13

申请号：US17851596

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpil SON

IPC: G11C29/12 ,  G11C29/10 ,  G11C29/36

Abstract: A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop.

公开(公告)号：US20210365203A1

公开(公告)日：2021-11-25

申请号：US17213732

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Jongpil SON ,  Kyomin SOHN

IPC: G06F3/06

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

公开(公告)号：US20170352433A1

公开(公告)日：2017-12-07

申请号：US15450588

申请日：2017-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongpil SON ,  Hosung SONG ,  Wonchang JUNG

IPC: G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: G11C29/023 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/787 ,  G11C29/808 ,  G11C29/81 ,  G11C29/846 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.