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公开(公告)号：US11678437B2
公开(公告)日：2023-06-13
申请号：US17210907
申请日：2021-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Hyun Seok , Gyu Chae Lee , Jeong Hyeon Cho
CPC classification number: H05K1/181 , H01L25/18 , H05K1/117 , H05K2201/09227 , H05K2201/09509 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H05K2201/10734
Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.
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公开(公告)号：US09786354B2
公开(公告)日：2017-10-10
申请号：US15269170
申请日：2016-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Hyun Seok , Do-Hyung Kim , Won-Hyung Song , Young-Ho Lee
IPC: H05K7/00 , G11C11/4093 , G11C5/04 , G11C7/02 , G11C7/10
CPC classification number: G11C11/4093 , G11C5/04 , G11C7/02 , G11C7/10 , G11C2207/105
Abstract: A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.
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公开(公告)号：US12022619B2
公开(公告)日：2024-06-25
申请号：US18309413
申请日：2023-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Hyun Seok , Gyu Chae Lee , Jeong Hyeon Cho
CPC classification number: H05K1/181 , H01L25/18 , H05K1/117 , H05K2201/09227 , H05K2201/09509 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H05K2201/10734
Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.
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Patent Agency Ranking
公开(公告)号：US09406369B2
公开(公告)日：2016-08-02
申请号：US14325867
申请日：2014-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hyun Seok , Dohyung Kim , Kwangseop Kim , Young-Ho Lee
IPC: H01L23/34 , G11C11/401 , G11C5/02 , G11C5/04
CPC classification number: G11C11/401 , G11C5/025 , G11C5/04
Abstract: A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.
Abstract translation: 存储模块包括印刷电路板; 第一存储器芯片，沿着第一列与印刷电路板的长轴平行设置; 第二存储器芯片沿着第二列与印刷电路板的长轴平行布置; 以及设置在所述第一存储器芯片和所述第二存储器芯片之间的无源元件，其中所述无源元件连接在所述第一存储器芯片和所述第二存储器芯片中的每一个的输入/输出引脚之间。
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公开(公告)号：US08951048B2
公开(公告)日：2015-02-10
申请号：US13742551
申请日：2013-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hyun Seok , Kyoung-Sun Kim
CPC classification number: H05K1/117 , H01L2924/0002 , H05K2201/094 , H01L2924/00
Abstract: A printed circuit board (PCB) includes a substrate body including a circuit wiring layer; tap terminals provided at a surface of the substrate body and in a peripheral region of the substrate body and electrically connected to the circuit wiring layer; and plating wires corresponding to respective tap terminals, each plating wire extending from an end portion of its respective tap terminal toward an edge of the substrate body and having a line width smaller than a line width of the tap terminal. For at least a first tap terminal, the tap terminal shares an edge with an edge of its respective plating wire. A second tap terminal adjacent the first tap terminal is positioned outside a circle having a radius that equals a length of the plating wire and having a center at a point along the shared edge where the plating wire and first tap terminal connect.
Abstract translation: 印刷电路板（PCB）包括：基板主体，包括电路布线层; 抽头端子，其设置在所述基板主体的表面和所述基板主体的周边区域中，并电连接到所述电路布线层; 以及对应于各个抽头端子的电镀线，每个电镀线从其各个抽头端子的端部朝向衬底主体的边缘延伸并且具有小于抽头端子的线宽的线宽。 对于至少第一抽头端子，抽头端子与其各自电镀线的边缘共享边缘。 与第一抽头端子相邻的第二抽头端子位于具有等于电镀线长度的半径的圆的外侧，并且具有沿着电镀线和第一抽头端子连接的共享边缘的点的中心。
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公开(公告)号：US12075560B2
公开(公告)日：2024-08-27
申请号：US17741510
申请日：2022-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hyun Seok , Yong-Jin Kim , Kyeongseon Park , Hwanwook Park
CPC classification number: H05K1/025 , H01P3/08 , H01L25/18 , H05K1/117 , H05K1/18 , H05K2201/09227 , H05K2201/09245 , H05K2201/09336 , H05K2201/09672 , H05K2201/10159 , H05K2201/10515 , H05K2201/10522 , H05K2201/10545
Abstract: A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer. A second layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane. The second signal lines have linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.
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公开(公告)号：US20230269876A1
公开(公告)日：2023-08-24
申请号：US18309413
申请日：2023-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Hyun Seok , Gyu Chae Lee , Jeong Hyeon Cho
CPC classification number: H05K1/181 , H01L25/18 , H05K2201/09227 , H05K2201/10159 , H05K2201/09509 , H05K2201/10545 , H05K2201/10734 , H05K1/117
Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal may receive the first signal from the buffer at the same time. The first connection terminal may be closer to the buffer as compared with the second connection terminal. The third connection terminal may be closer to the buffer as compared with the fourth connection terminal.
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公开(公告)号：US20230065980A1
公开(公告)日：2023-03-02
申请号：US17741510
申请日：2022-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hyun Seok , Yong-Jin Kim , Kyeongseon Park , Hwanwook Park
Abstract: A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer. A second layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane. The second signal lines have linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.
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