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公开(公告)号:US11785710B2
公开(公告)日:2023-10-10
申请号:US17947397
申请日:2022-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号:US11523506B2
公开(公告)日:2022-12-06
申请号:US17345815
申请日:2021-06-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaekwang Lee , Dongmin Jang , Hwanwook Park , Jaeseok Jang , Dohyung Kim
Abstract: A module board is provided. The module board includes a plurality of first left terminals and a plurality of first right terminals. Each of the plurality of first left terminals includes a left upper body, a left lower body, and a left lower bar which are connected to one another and sequentially provided, each of the plurality of first right terminals includes a right upper body, a right lower body, and a right lower bar which are connected to one another and sequentially provided, and a first width of each of the left upper body and the right upper body is greater than a second width of each of the left lower bar and the right lower bar.
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公开(公告)号:US12063736B2
公开(公告)日:2024-08-13
申请号:US18240619
申请日:2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号:US11974391B2
公开(公告)日:2024-04-30
申请号:US17573156
申请日:2022-01-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongyoon Seo , Hwanwook Park , Dohyung Kim , Bora Kim , Seungyeong Lee , Wonseop Lee , Yunho Lee , Yejin Cho
IPC: H05K1/02 , G11C11/4076 , H05K1/11
CPC classification number: H05K1/0268 , G11C11/4076 , H05K1/11 , H05K1/116 , H05K2201/09445 , H05K2201/09481 , H05K2201/10159
Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.
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公开(公告)号:US20230413424A1
公开(公告)日:2023-12-21
申请号:US18240619
申请日:2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop LEE , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , H01L25/112 , H01L25/0657 , H05K1/025 , G11C5/063 , G11C8/18 , G06F13/4086 , G11C5/04 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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公开(公告)号:US12075560B2
公开(公告)日:2024-08-27
申请号:US17741510
申请日:2022-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Hyun Seok , Yong-Jin Kim , Kyeongseon Park , Hwanwook Park
CPC classification number: H05K1/025 , H01P3/08 , H01L25/18 , H05K1/117 , H05K1/18 , H05K2201/09227 , H05K2201/09245 , H05K2201/09336 , H05K2201/09672 , H05K2201/10159 , H05K2201/10515 , H05K2201/10522 , H05K2201/10545
Abstract: A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer. A second layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane. The second signal lines have linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.
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公开(公告)号:US11812547B2
公开(公告)日:2023-11-07
申请号:US17356940
申请日:2021-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongyoon Seo , Sangkeun Kwak , Dohyung Kim , Kyeongseon Park , Hwanwook Park , Wonseop Lee , Daae Heo
CPC classification number: H05K1/0263 , H05K1/0296 , H05K1/142 , H05K2201/10159
Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.
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公开(公告)号:US11758652B2
公开(公告)日:2023-09-12
申请号:US17360417
申请日:2021-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongyoon Seo , Geunje Park , Dohyung Kim , Hwanwook Park , Dongmin Jang , Jaeseok Jang
CPC classification number: H05K1/111 , H05K1/181 , H05K2201/09745
Abstract: A printed circuit board (PCB) includes: an insulation substrate; a first pad on the insulation substrate; and a second pad on the insulation substrate and spaced apart from the first pad, wherein the second pad has a size substantially the same as a size of the first pad, wherein the first pad includes a first recess configured to receive a first electrode of a passive element, wherein the second pad includes a second recess receiving a second electrode of the passive element, wherein the first recess has a depth substantially the same as a thickness of the first pad, wherein the second recess has a depth substantially the same as a thickness of the second pad, wherein each of the first recess and the second recess exposes an upper surface of the insulation substrate.
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公开(公告)号:US20230065980A1
公开(公告)日:2023-03-02
申请号:US17741510
申请日:2022-05-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Hyun Seok , Yong-Jin Kim , Kyeongseon Park , Hwanwook Park
Abstract: A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer. A second layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane. The second signal lines have linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.
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公开(公告)号:US11477880B2
公开(公告)日:2022-10-18
申请号:US17337850
申请日:2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
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