公开(公告)号：US20230187446A1

公开(公告)日：2023-06-15

申请号：US18082617

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Seok JO ,  Jae-Hyun LEE ,  Jong-Han LEE ,  Hong-Bae PARK ,  Dong-Soo LEE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823864 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/823871 ,  H01L29/517

Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.

公开(公告)号：US20190157410A1

公开(公告)日：2019-05-23

申请号：US16030291

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Hyuk Yim ,  Wan-Don KIM ,  Jong-Han LEE ,  Hyung-Suk JUNG ,  Sang-Jin HYUN

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.