公开(公告)号：US09373380B2

公开(公告)日：2016-06-21

申请号：US14034994

申请日：2013-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun Kim

IPC: G11C11/00 ,  G11C8/16 ,  G11C7/10 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C8/16 ,  G06F13/1694 ,  G11C7/1075 ,  G11C11/005 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/0009 ,  G11C14/0018 ,  G11C14/0036

Abstract: A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells. The first interface circuit is configured to receive a DRAM interface signals, and the second interface circuit is configured to receive a flash memory interface signals.

Abstract translation: 提供一种半导体存储器件，其包括被配置为连接到第一处理器并包括第一接口电路的第一端口; 第二端口，被配置为连接到第二处理器并且包括第二接口电路; 以及包括共同连接到第一和第二端口的第一存储区域的存储单元阵列。 第一存储区包括多个磁阻随机存取存储单元。 第一接口电路被配置为接收DRAM接口信号，并且第二接口电路被配置为接收闪存接口信号。

公开(公告)号：US10162771B2

公开(公告)日：2018-12-25

申请号：US15346342

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun Kim ,  Won-Hyung Song

IPC: G11C11/408 ,  G06F13/16 ,  G11C11/4096 ,  G06F17/50 ,  G06F13/40 ,  G11C5/02 ,  G11C7/10

Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.