公开(公告)号：US20220122933A1

公开(公告)日：2022-04-21

申请号：US17460873

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.

公开(公告)号：US20230326847A1

公开(公告)日：2023-10-12

申请号：US18334546

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/2105 ,  H01L2224/24146 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B43/27

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

公开(公告)号：US20220130846A1

公开(公告)日：2022-04-28

申请号：US17239829

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon KIM ,  Jaeho AHN ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L27/11556 ,  H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/78

Abstract: A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.

公开(公告)号：US20220139855A1

公开(公告)日：2022-05-05

申请号：US17328176

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joon-Sung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/10

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US20220130861A1

公开(公告)日：2022-04-28

申请号：US17573015

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho AHN ,  Woosung YANG ,  Joonsung LIM ,  Sungmin HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

公开(公告)号：US20220102334A1

公开(公告)日：2022-03-31

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon KIM ,  Jaeho AHN ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.