公开(公告)号：US20240321831A1

公开(公告)日：2024-09-26

申请号：US18606534

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Insup SHIN ,  Hyeongmun KANG ,  Yuduk KIM ,  Seungwoo SIM

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05012 ,  H01L2224/06131 ,  H01L2224/16148 ,  H01L2224/32148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/1436 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a plurality of conductive front pads on lower surfaces of the plurality of second semiconductor chips, a plurality of conductive rear pads attached to an upper surface of the first semiconductor chip and an upper surface of each of the plurality of second semiconductor chips, and including a plurality of first bonding pads and a plurality of second bonding pads in different regions, and a plurality of chip connection terminals between the plurality of conductive front pads and the plurality of conductive rear pads, wherein each of the plurality of second bonding pads includes a supporting part configured to support each of the plurality of chip connection terminals, and a fixing part protruding from an upper surface of the supporting part.

公开(公告)号：US20220367367A1

公开(公告)日：2022-11-17

申请号：US17517798

申请日：2021-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongmun KANG ,  Woodong LEE ,  Insup SHIN ,  Youngwoo LIM

IPC: H01L23/538 ,  H01L25/065

Abstract: A carrier structure including semiconductor chip stack structures; and a carrier tape including a plurality of pockets respectively accommodating the semiconductor chip stack structures, wherein each of the plurality of pockets includes a bottom surface, first sidewalls in four corner regions of each of the plurality of pockets, and second sidewalls between adjacent first sidewalls, each of the first sidewalls has a first portion having a first inclination angle and a second portion on the first portion and having a second inclination angle, the second inclination angle being greater than the first inclination angle, and vertices of lower surfaces of the semiconductor chip stack structures are in contact with the first sidewalls.

公开(公告)号：US20190067258A1

公开(公告)日：2019-02-28

申请号：US15960698

申请日：2018-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young KIM ,  PYOUNGWAN KIM ,  HYUNKI KIM ,  Junwoo PARK ,  Sangsoo KIM ,  Seung Hwan KIM ,  Sung-Kyu PARK ,  Insup SHIN

IPC: H01L25/11 ,  H01L25/00

CPC classification number: H01L25/117 ,  H01L21/561 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.

公开(公告)号：US20240290754A1

公开(公告)日：2024-08-29

申请号：US18433075

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Yu-Duk KIM ,  Hyeongmun KANG ,  Insup SHIN ,  Gunho CHANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/182

Abstract: Provided is a semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips on the first semiconductor chip, and a dummy chip on the plurality of second semiconductor chips, wherein each of the plurality of second semiconductor chips has a first width, and wherein the dummy chip has a second width smaller than the first width.

公开(公告)号：US20210398947A1

公开(公告)日：2021-12-23

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup SHIN ,  Hyeongmun KANG ,  Jungmin KO ,  Hwanyoung CHOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.