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    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220139881A1

    公开(公告)日：2022-05-05

    申请号：US17574953

    申请日：2022-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjun SONG ,  Eunkyul OH ,  Hyeongmun KANG ,  Jungmin KO

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

    CARRIER STRUCTURE INCLUDING POCKETS FOR ACCOMMODATING SEMICONDUCTOR CHIP STACK STRUCTURE
    2.
    发明申请
    CARRIER STRUCTURE INCLUDING POCKETS FOR ACCOMMODATING SEMICONDUCTOR CHIP STACK STRUCTURE 有权

    公开(公告)号：US20220367367A1

    公开(公告)日：2022-11-17

    申请号：US17517798

    申请日：2021-11-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyeongmun KANG ,  Woodong LEE ,  Insup SHIN ,  Youngwoo LIM

    IPC: H01L23/538 ,  H01L25/065

    Abstract: A carrier structure including semiconductor chip stack structures; and a carrier tape including a plurality of pockets respectively accommodating the semiconductor chip stack structures, wherein each of the plurality of pockets includes a bottom surface, first sidewalls in four corner regions of each of the plurality of pockets, and second sidewalls between adjacent first sidewalls, each of the first sidewalls has a first portion having a first inclination angle and a second portion on the first portion and having a second inclination angle, the second inclination angle being greater than the first inclination angle, and vertices of lower surfaces of the semiconductor chip stack structures are in contact with the first sidewalls.

    SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS
    5.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS 有权

    公开(公告)号：US20220148994A1

    公开(公告)日：2022-05-12

    申请号：US17584776

    申请日：2022-01-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehyeong KIM ,  Hyeongmun KANG ,  Seungduk BAEK

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10

    Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210265315A1

    公开(公告)日：2021-08-26

    申请号：US17030588

    申请日：2020-09-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjun SONG ,  Eunkyul OH ,  Hyeongmun KANG ,  Jungmin KO

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

    Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

    CHIP-STACKED SEMICONDUCTOR PACKAGE WITH INCREASED PACKAGE RELIABILITY
    8.
    发明申请
    CHIP-STACKED SEMICONDUCTOR PACKAGE WITH INCREASED PACKAGE RELIABILITY 有权

    公开(公告)号：US20210398947A1

    公开(公告)日：2021-12-23

    申请号：US17352757

    申请日：2021-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Insup SHIN ,  Hyeongmun KANG ,  Jungmin KO ,  Hwanyoung CHOI

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

    SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS
    9.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS 有权

    公开(公告)号：US20210175134A1

    公开(公告)日：2021-06-10

    申请号：US17010059

    申请日：2020-09-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehyeong KIM ,  Hyeongmun KANG ,  Seungduk BAEK

    IPC: H01L21/66 ,  H01L23/00 ,  H01L25/18

    Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

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