公开(公告)号：US20190067258A1

公开(公告)日：2019-02-28

申请号：US15960698

申请日：2018-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young KIM ,  PYOUNGWAN KIM ,  HYUNKI KIM ,  Junwoo PARK ,  Sangsoo KIM ,  Seung Hwan KIM ,  Sung-Kyu PARK ,  Insup SHIN

IPC: H01L25/11 ,  H01L25/00

CPC classification number: H01L25/117 ,  H01L21/561 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.

公开(公告)号：US20210375831A1

公开(公告)日：2021-12-02

申请号：US17399233

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Kyungsuk OH ,  Hyunki KIM ,  Yongkwan LEE ,  Sangsoo KIM ,  Seungkon MOK ,  Junyoung OH ,  Changyoung YOO

IPC: H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

公开(公告)号：US20230119406A1

公开(公告)日：2023-04-20

申请号：US17842262

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pilsung CHOI ,  Donguk KWON ,  Sangsoo KIM ,  Wooram MYUNG ,  Jiwon SHIN ,  Sehun AHN

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.

公开(公告)号：US20210202352A1

公开(公告)日：2021-07-01

申请号：US17203084

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki KIM ,  Sangsoo KIM ,  Seung Hwan KIM ,  Kyung Suk OH ,  Yongkwan LEE ,  Jongho LEE

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/07

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.