公开(公告)号：US11201166B2

公开(公告)日：2021-12-14

申请号：US16582240

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US10453821B2

公开(公告)日：2019-10-22

申请号：US15966673

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Tae Lee ,  Han Kim ,  Hyung Joon Kim

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

Abstract: A connection system of semiconductor packages includes: a printed circuit board having a first surface, and a second surface, opposing the first surface; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; and a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures. The first semiconductor package includes an application processor (AP) and a power management integrated circuit (PMIC) disposed side by side, and the second semiconductor package includes a memory.

公开(公告)号：US10425568B2

公开(公告)日：2019-09-24

申请号：US15653677

申请日：2017-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Won Kim ,  Hyung Joon Kim ,  Surng Kyo Oh ,  Cheul Hee Hahm ,  Weon Seok Heo ,  Ji Hyun Bae ,  Hae Kwang Lee ,  Dong Ryun Seok

IPC: H04N5/232 ,  H04N1/00 ,  H04N21/4363 ,  H04N21/442 ,  H04N5/44 ,  H04N21/4367 ,  H04N5/63

Abstract: A display device includes a first communication unit connected to one or more peripheral devices, a second communication unit that communicates with a remote controller, and a processor. If the processor is initialized in response to a power-on instruction through the second communication unit, the processor verifies whether a first peripheral device, which is selected as a source device that provides at least one source of video and audio signals, among the one or more peripheral devices is powered on within a first threshold time. If the first peripheral device is not powered on within the first threshold time, the processor transmits a power-on request for allowing the remote controller to power on the first peripheral device, to the remote controller through the second communication unit.

公开(公告)号：US10020318B2

公开(公告)日：2018-07-10

申请号：US15218610

申请日：2016-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Kim ,  BiO Kim ,  Hyung Joon Kim ,  Young Seon Son ,  Su Jin Shin ,  Jae Young Ahn ,  Ju Mi Yun ,  HanMei Choi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/7926

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

公开(公告)号：US11335685B2

公开(公告)日：2022-05-17

申请号：US16693889

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hyung Joon Kim ,  Hyun Jung Lee

IPC: H01L27/108 ,  H01L27/11565

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

公开(公告)号：US11094709B2

公开(公告)日：2021-08-17

申请号：US16441657

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Jung Geun Jee

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11568

Abstract: A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

公开(公告)号：US20200381446A1

公开(公告)日：2020-12-03

申请号：US16582240

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung CHOI ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US10825833B1

公开(公告)日：2020-11-03

申请号：US16930711

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/532

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US10756107B2

公开(公告)日：2020-08-25

申请号：US16203790

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/1157

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US10756023B2

公开(公告)日：2020-08-25

申请号：US15905046

申请日：2018-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Kim ,  Hyung Joon Kim

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/58 ,  H01L23/538 ,  H01L23/367

Abstract: A semiconductor package includes a connection member and a supporting member. The connection member has first and second surfaces opposing each other and a redistribution layer. The supporting member is disposed on the first surface of the connection member, has a first through-hole and a second through-hole spaced apart from each other, and has a blocking layer disposed on at least an inner surface of the second through-hole. A semiconductor chip is disposed in the first through-hole and has connection pads connected to the redistribution layer. At least one passive component is disposed in the second through-hole and has connection terminals connected to the redistribution layer. An encapsulant encapsulates the semiconductor chip and the at least one passive component in the first and second through-holes, respectively. An electromagnetic band-gap (EBG) structure is embedded in the supporting member.