公开(公告)号：US11723203B2

公开(公告)日：2023-08-08

申请号：US17540688

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US11201166B2

公开(公告)日：2021-12-14

申请号：US16582240

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US20200381446A1

公开(公告)日：2020-12-03

申请号：US16582240

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung CHOI ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US10453707B2

公开(公告)日：2019-10-22

申请号：US15791795

申请日：2017-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Seok Cho ,  Hyung Joon Kim ,  Jung Ho Kim ,  Joong Yun Ra ,  Bi O Kim ,  Jae Young Ahn ,  Ki Yong Oh ,  Sung Hae Lee

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/8239 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/108 ,  H01L27/11582

Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.