SWITCHING REGULATOR, SYSTEM-ON-CHIP INCLUDING THE SWITCHING REGULATOR, AND OPERATING METHOD OF THE SWITCHING REGULATOR

    公开(公告)号:US20230231473A1

    公开(公告)日:2023-07-20

    申请号:US18065164

    申请日:2022-12-13

    CPC classification number: H02M3/07 G06F1/26 H02M1/0009

    Abstract: A switching regulator, system-on-chip including the switching regulator, and operating method of the switching regulator are provided. The switching regulator comprises a first inductor having a first end connected to a first node and a second end connected to an output terminal, a second inductor having a first end connected to a second node and a second end connected to the output terminal, a flying capacitor having a first end connected to the first node and a second end connected to the second node, and control circuitry configured to at each of first through fourth times control the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch to cause the flying capacitor to store a voltage corresponding to a difference between currents flowing in the first inductor and the second inductor.

    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

    公开(公告)号:US20180129599A1

    公开(公告)日:2018-05-10

    申请号:US15713052

    申请日:2017-09-22

    Inventor: Hyun Sik KIM

    Abstract: A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL) mapping table, which includes a physical page number (PPN) of a flash memory and a logical page number (LPN) corresponding to the PPN; a central processing unit (CPU) accessing a memory mapped address space to which a logical address corresponding to the LPN is allocated; and an LPN translator receiving the logical address from the CPU, extracting an LPN corresponding to the logical address, reading, from the memory, the FTL mapping table corresponding to the extracted LPN, extracting a PPN corresponding to the extracted LPN, and transmitting the extracted PPN to the CPU.

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