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1.
公开(公告)号:US20180204679A1
公开(公告)日:2018-07-19
申请号:US15875386
申请日:2018-01-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chan KWAK , Hyun Sik KIM , Jong Wook ROH , Kyoung-Seok MOON , Hyeon Cheol PARK , Yoon Chul SON , Daejin YANG , Doh Won JUNG , Youngjin CHO
CPC classification number: H01G4/30 , C04B35/47 , C04B35/62805 , C04B35/62815 , C04B2235/3201 , C04B2235/3208 , C04B2235/3251 , C04B2235/3255 , C04B2235/6582 , C04B2235/6588 , C04B2235/781 , C04B2235/79 , C04B2235/85 , C04B2237/346 , C04B2237/68 , H01C7/008 , H01C7/1006 , H01C7/18 , H01C17/06533 , H01G4/1218 , H01G4/1227 , H01G4/1236 , H01G4/1245 , H01G4/14 , H01G4/232 , H01G4/248
Abstract: A dielectric composite including a plurality of crystal grains including a semiconductor or conductive material, and a grain boundary insulation layer between the crystal grains, wherein the grain boundary insulation layer includes a two-dimensional layered material covering at least a portion of a surface of at least one of the crystal grains, and a multi-layered capacitor and an electronic device including the same.
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2.
公开(公告)号:US20230231473A1
公开(公告)日:2023-07-20
申请号:US18065164
申请日:2022-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeong Hyun CHO , Hyun Sik KIM , Hong Hyun BAE
CPC classification number: H02M3/07 , G06F1/26 , H02M1/0009
Abstract: A switching regulator, system-on-chip including the switching regulator, and operating method of the switching regulator are provided. The switching regulator comprises a first inductor having a first end connected to a first node and a second end connected to an output terminal, a second inductor having a first end connected to a second node and a second end connected to the output terminal, a flying capacitor having a first end connected to the first node and a second end connected to the second node, and control circuitry configured to at each of first through fourth times control the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch to cause the flying capacitor to store a voltage corresponding to a difference between currents flowing in the first inductor and the second inductor.
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3.
公开(公告)号:US20190304685A1
公开(公告)日:2019-10-03
申请号:US16033392
申请日:2018-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyun Sik KIM , Yoon Chul SON , Kyoung-Seok MOON , Daejin YANG , Chan KWAK
Abstract: Disclosed are a dielectric material, a multi-layered capacitor, and an electronic device including the same. The dielectric material includes a dielectric material particle represented by ADO3, wherein A includes Sr, Ba, Ca, Pb, K, Na, or a combination thereof, D includes Ti, Zr, Mg, Nb, Ta, or a combination thereof, the dielectric material particle includes about 2.5 moles to about 4 moles of the donor element, based on 100 moles of D, and a diameter of the dielectric material particle is in a range of from about 100 nanometers to about 300 nanometers.
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4.
公开(公告)号:US20190189345A1
公开(公告)日:2019-06-20
申请号:US16100285
申请日:2018-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyoung-Seok MOON , Hyeon Cheol PARK , Chan KWAK , Hyun Sik KIM , Daejin YANG , Youngjin CHO
CPC classification number: H01G4/1227 , H01G4/008 , H01G4/30
Abstract: A ceramic dielectric includes a plurality of semi-conductive grains including a semiconductor oxide including barium (Ba), titanium (Ti), and a rare earth element. A ceramic dielectric also includes an insulative oxide located between adjacent semiconductor grains and an acceptor element including manganese (Mn), magnesium (Mg), aluminum (Al), iron (Fe), scandium (Sc), gallium (Ga), or a combination thereof, a method of manufacturing the ceramic dielectric, and a ceramic electronic component, and an electronic device including the ceramic dielectric.
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公开(公告)号:US20180129599A1
公开(公告)日:2018-05-10
申请号:US15713052
申请日:2017-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyun Sik KIM
IPC: G06F12/02 , G06F12/0873 , G06F12/1009
CPC classification number: G06F12/0246 , G06F12/0873 , G06F12/1009 , G06F2212/1024 , G06F2212/7201
Abstract: A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL) mapping table, which includes a physical page number (PPN) of a flash memory and a logical page number (LPN) corresponding to the PPN; a central processing unit (CPU) accessing a memory mapped address space to which a logical address corresponding to the LPN is allocated; and an LPN translator receiving the logical address from the CPU, extracting an LPN corresponding to the logical address, reading, from the memory, the FTL mapping table corresponding to the extracted LPN, extracting a PPN corresponding to the extracted LPN, and transmitting the extracted PPN to the CPU.
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