公开(公告)号：US12108420B2

公开(公告)日：2024-10-01

申请号：US17508537

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbong Ryu ,  Hyeongjin Kim ,  Jongmoon Park ,  Seongha Lee ,  Seoyeon Hong

IPC: H04W72/51 ,  H04W76/14 ,  H04W76/15 ,  H04W84/12 ,  H04W88/06

CPC classification number: H04W72/51 ,  H04W76/14 ,  H04W76/15 ,  H04W84/12 ,  H04W88/06

Abstract: Disclosed is an electronic device including a wireless communication circuit, and a processor operably connected to the wireless communication circuit, wherein the processor is configured to identify a first channel for communication with an access point (AP) based on wireless fidelity (Wi-Fi) and a second channel for direct communication with an external electronic device based on Wi-Fi direct, reconfigure a capability of the electronic device related to direct communication with the external electronic device when the first channel and the second channel are different, and transmit information about the reconfigured capability of the electronic device to the external electronic device through the wireless communication circuit.

公开(公告)号：US12149251B2

公开(公告)日：2024-11-19

申请号：US18156106

申请日：2023-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongjin Kim ,  Hyohyun Nam ,  Dongki Kim ,  Dae Young Lee

IPC: H03K5/00 ,  H03K17/56 ,  H03K5/08

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system or a 6th-Generation (6G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system. A frequency multiplier of a wireless communication system is provided. The frequency multiplier includes an input circuit to which a local oscillator (LO) signal is input, a multiplier circuit having one end connected to the input circuit and another end connected to a lower terminal of a load circuit, a load circuit having an upper terminal connected to a voltage controller, and a voltage controller configured between the upper terminal of the load circuit and an input power source, wherein the voltage controller may be configured to drop a voltage between the input power source and the upper terminal of the load circuit and reinput a feedback voltage based on an upper terminal voltage of the load circuit to the voltage controller, and a method of multiplying a frequency using the same.

公开(公告)号：US20230062069A1

公开(公告)日：2023-03-02

申请号：US17860800

申请日：2022-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhwan Son ,  Hyeongjin Kim ,  Seungjun Shin ,  Joongshik Shin ,  Minsoo Shin ,  Jeehoon Han

IPC: G11C16/04 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.

公开(公告)号：US20250126789A1

公开(公告)日：2025-04-17

申请号：US18661135

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsoo Shin ,  Joongshik Shin ,  Hyeongjin Kim ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A three-dimensional semiconductor memory device includes a plurality of peripheral circuit structures on a substrate, a plurality of stacked structures, each the plurality of stacked structures including a plurality of gate electrodes stacked on the plurality of peripheral circuit structure in a first direction perpendicular to a lower surface of the substrate, and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate, a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction, the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure; and an internal insulating layer surrounding a side surface of each of the plurality of support patterns.