公开(公告)号：US12041188B2

公开(公告)日：2024-07-16

申请号：US17394613

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoung Shin ,  Sung Ung Kwak ,  Ji-Sung Kim ,  Shin-Wuk Kang

IPC: H04L29/00 ,  G11C7/06 ,  G11C8/10 ,  H03M1/66 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/3278 ,  G11C7/06 ,  G11C8/10 ,  H03M1/662 ,  H04L9/0866

Abstract: A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.

公开(公告)号：US12040805B2

公开(公告)日：2024-07-16

申请号：US17853148

申请日：2022-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung Shin ,  Bora Kim ,  Junho Kim

IPC: G06F7/58 ,  H03K19/173 ,  H03L7/081 ,  H03L7/083 ,  H03L7/099 ,  H03L7/107

CPC classification number: H03L7/0996 ,  G06F7/582 ,  H03K19/1737 ,  H03L7/0818 ,  H03L7/083 ,  H03L7/1077

Abstract: A random number generator includes a ring oscillator, an inversion selecting circuit, and controller. The ring oscillator includes an inverter chain having at least one inverter and generates an output signal. The inversion selecting circuit controlling a phase inverter configured to invert a signal of the inverter chain. The controller is configured to operate the inversion selecting circuit to provide an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and operate the inversion selecting circuit to not provide the output of the phase inverter during a second operation mode for generating a random number.

公开(公告)号：US11488642B2

公开(公告)日：2022-11-01

申请号：US17376401

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung Shin

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02 ,  G11C7/04

Abstract: Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.

公开(公告)号：US10957395B2

公开(公告)日：2021-03-23

申请号：US16828099

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoung Shin ,  Ji-Sung Kim ,  Hyun-Jin Shin

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

Abstract: A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time.

公开(公告)号：US20190115077A1

公开(公告)日：2019-04-18

申请号：US16003848

申请日：2018-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung Shin ,  Myeonghee Oh

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C11/4074 ,  G11C7/04 ,  H01L29/788

Abstract: A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.