公开(公告)号：US20200083220A1

公开(公告)日：2020-03-12

申请号：US16382439

申请日：2019-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghwa Park ,  Hongbae Park ,  Jaehyun Lee ,  Jonghan Lee ,  Dabok Jeong ,  Minseok Jo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.

公开(公告)号：US08766366B2

公开(公告)日：2014-07-01

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-seok Hong

IPC: H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。

公开(公告)号：US11289478B2

公开(公告)日：2022-03-29

申请号：US16382439

申请日：2019-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghwa Park ,  Hongbae Park ,  Jaehyun Lee ,  Jonghan Lee ,  Dabok Jeong ,  Minseok Jo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.

公开(公告)号：USRE49538E1

公开(公告)日：2023-05-30

申请号：US17070488

申请日：2020-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28 ,  H01L29/49 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.