公开(公告)号：US08766366B2

公开(公告)日：2014-07-01

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-seok Hong

IPC: H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。

公开(公告)号：US09236313B2

公开(公告)日：2016-01-12

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

公开(公告)号：US08772115B2

公开(公告)日：2014-07-08

申请号：US13770709

申请日：2013-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HyeokJun Son ,  Sangjin Hyun ,  Sangbom Kang ,  SungKee Han ,  Sughun Hong ,  Hyung-seok Hong

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.

Abstract translation: 可以通过包括在具有第一区域和第二区域的衬底上形成第一栅极绝缘层的方法来制造包括选择性氮化栅极绝缘层的半导体器件，在第一栅极绝缘层上进行氮化处理，去除第一栅极绝缘层 栅极绝缘层，以从第一区域的至少一部分露出至少一部分基板，在至少基板的第一区域的暴露部分上形成第二栅极绝缘层，热处理第一和第二栅极绝缘层 层，在第一和第二栅极绝缘层上形成高k电介质，并在高k电介质上形成金属栅电极。

公开(公告)号：US20150093888A1

公开(公告)日：2015-04-02

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/51

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Abstract translation: 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US20130316525A1

公开(公告)日：2013-11-28

申请号：US13770709

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HyeokJun Son ,  Sangjin Hyun ,  Sangbom Kang ,  SungKee Han ,  Sughun Hong ,  Hyung-seok Hong

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.

Abstract translation: 可以通过包括在具有第一区域和第二区域的衬底上形成第一栅极绝缘层的方法来制造包括选择性氮化栅极绝缘层的半导体器件，在第一栅极绝缘层上进行氮化处理，去除第一栅极绝缘层 栅极绝缘层，以从第一区域的至少一部分露出至少一部分基板，在至少基板的第一区域的暴露部分上形成第二栅极绝缘层，热处理第一和第二栅极绝缘层 层，在第一和第二栅极绝缘层上形成高k电介质，并在高k电介质上形成金属栅电极。