公开(公告)号：US20210391384A1

公开(公告)日：2021-12-16

申请号：US17460635

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/10

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20210159272A1

公开(公告)日：2021-05-27

申请号：US16887541

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L23/522 ,  H01L23/528

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

公开(公告)号：US20190088864A1

公开(公告)日：2019-03-21

申请号：US16044666

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Na CHO ,  Hye-Ji YOON ,  O-Ik KWON

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

公开(公告)号：US20230397438A1

公开(公告)日：2023-12-07

申请号：US18452886

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Na CHO ,  Bok-Yeon WON ,  Oik KWON

IPC: H10B61/00 ,  H01L23/528 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H01L23/5283 ,  H01L23/5226 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.