公开(公告)号：US20220115383A1

公开(公告)日：2022-04-14

申请号：US17237208

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-CHUL YOON ,  SUNGUN KWON ,  HANSEUNG KWAK ,  JIHEE KIM ,  SUNGHOON CHOI

IPC: H01L27/108

Abstract: Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

公开(公告)号：US20250159873A1

公开(公告)日：2025-05-15

申请号：US18747036

申请日：2024-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG SEOK PARK ,  HYUN-CHUL YOON ,  ChangSik YOO ,  JEONGDON IHM

IPC: H10B12/00

Abstract: A semiconductor memory device includes a peripheral circuit structure, and a cell array structure provided thereon and including a plurality of cell array regions and an upper peripheral region provided between a plurality of cell array regions. A cell array structure includes vertical cell transistors, first vertical peripheral transistors, and second vertical peripheral transistors. Each of vertical cell transistors, a first vertical peripheral transistors, and a second vertical peripheral transistors has a channel extending along a third direction parallel to an arrangement direction of a peripheral circuit structure and a cell array structure. Vertical cell transistors are disposed in a cell array region and have a first polarity. First vertical peripheral transistors are disposed in an upper peripheral region and have a first polarity. Second vertical peripheral transistors are disposed in an upper peripheral region and have a second polarity different from a first polarity.

公开(公告)号：US20150003146A1

公开(公告)日：2015-01-01

申请号：US14253353

申请日：2014-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KICHUL CHUN ,  HYUN-CHUL YOON

IPC: G11C11/4094

CPC classification number: G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4091

Abstract: A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit lines toward a ground level and clamps the low-level bit line to a boosted sense ground voltage in response to a control signal. A sense amplifier control logic generates the control signal having a pulse interval. The low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.

Abstract translation: 提供半导体存储器件。 单元阵列包括连接到一对位线之一的DRAM单元。 位线读出放大器耦合到一对位线。 位线读出放大器将一对位线的低电平位线朝向接地电平放电，并且响应于控制信号将低电平位线钳位到升压检测接地电压。 读出放大器控制逻辑产生具有脉冲间隔的控制信号。 低电平位线在脉冲间隔内向地电平放电，脉冲间隔结束后，低电平位线被钳位到升压检测接地电压。

公开(公告)号：US20160233104A1

公开(公告)日：2016-08-11

申请号：US14976296

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAM-GUN KIM ,  JINYOUNG KIM ,  JONGCHEON KIM ,  CHANMl LEE ,  SUNGGIL CHOI ,  HYUN-CHUL YOON

IPC: H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11531

Abstract: A method of forming a semiconductor pattern can include providing an etching target layer. A hard mask pattern can be formed on the etching target layer using photolithography. First spacers can be formed on opposing sidewalls of the hard mask pattern and the hard mask pattern can be removed from between the first spacers to provide a first double patterning pattern self-aligned to the hard mask pattern. The planarization of top surfaces of the first double patterning pattern can be increased to provide a smoothed first double patterning pattern.

Abstract translation: 形成半导体图案的方法可以包括提供蚀刻目标层。 可以使用光刻法在蚀刻目标层上形成硬掩模图案。 可以在硬掩模图案的相对侧壁上形成第一间隔物，并且可以在第一间隔物之间​​移除硬掩模图案，以提供与硬掩模图案自对准的第一双重图案图案图案。 可以增加第一双图形图案的顶表面的平面化，以提供平滑的第一双图案图案。