公开(公告)号：US20170133266A1

公开(公告)日：2017-05-11

申请号：US15277636

申请日：2016-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAM-GUN KIM ,  CHAN-Ml LEE

IPC: H01L21/768 ,  H01L27/11 ,  H01L27/108 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/108 ,  H01L27/11 ,  H01L28/00

Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.

公开(公告)号：US20160233104A1

公开(公告)日：2016-08-11

申请号：US14976296

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAM-GUN KIM ,  JINYOUNG KIM ,  JONGCHEON KIM ,  CHANMl LEE ,  SUNGGIL CHOI ,  HYUN-CHUL YOON

IPC: H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11531

Abstract: A method of forming a semiconductor pattern can include providing an etching target layer. A hard mask pattern can be formed on the etching target layer using photolithography. First spacers can be formed on opposing sidewalls of the hard mask pattern and the hard mask pattern can be removed from between the first spacers to provide a first double patterning pattern self-aligned to the hard mask pattern. The planarization of top surfaces of the first double patterning pattern can be increased to provide a smoothed first double patterning pattern.

Abstract translation: 形成半导体图案的方法可以包括提供蚀刻目标层。 可以使用光刻法在蚀刻目标层上形成硬掩模图案。 可以在硬掩模图案的相对侧壁上形成第一间隔物，并且可以在第一间隔物之间​​移除硬掩模图案，以提供与硬掩模图案自对准的第一双重图案图案图案。 可以增加第一双图形图案的顶表面的平面化，以提供平滑的第一双图案图案。