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公开(公告)号:US11271038B2
公开(公告)日:2022-03-08
申请号:US17027980
申请日:2020-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myoungsu Son , Seung Pil Ko , Jung Hyuk Lee , Shinhee Han , Gwan-Hyeob Koh , Yoonjong Song
IPC: H01L27/22 , H01L43/02 , H01L43/12 , H01L43/08 , H01L23/522
Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.
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公开(公告)号:US11158671B2
公开(公告)日:2021-10-26
申请号:US16435915
申请日:2019-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yong-Jae Kim , Kil-Ho Lee , Dae-Eun Jeong , Gwan-Hyeob Koh
IPC: H01L43/02 , H01L43/12 , H01L27/22 , H01L21/768
Abstract: A semiconductor device may include a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. A lower surface of the contact plug may have an area greater than that of an upper surface thereof, and the contact plug may include a capping pattern at least partially covering an upper surface of the conductive structure, a conductive pattern on the capping pattern, and an amorphous metal pattern on the conductive pattern.
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公开(公告)号:US20180342672A1
公开(公告)日:2018-11-29
申请号:US16055512
申请日:2018-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyu-Rie SIM , Dae-Hwan Kang , Gwan-Hyeob Koh
CPC classification number: H01L45/1233 , H01L27/2427 , H01L27/2481 , H01L43/08 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1675
Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
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公开(公告)号:US10818727B2
公开(公告)日:2020-10-27
申请号:US16161370
申请日:2018-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myoungsu Son , Seung Pil Ko , Jung Hyuk Lee , Shinhee Han , Gwan-Hyeob Koh , Yoonjong Song
IPC: H01L27/22 , H01L43/02 , H01L43/12 , H01L43/08 , H01L23/522
Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.
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公开(公告)号:US20190371998A1
公开(公告)日:2019-12-05
申请号:US16540146
申请日:2019-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dae-Shik Kim , Jeong-Heon Park , Gwan-Hyeob Koh
Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
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公开(公告)号:US09887354B2
公开(公告)日:2018-02-06
申请号:US15296423
申请日:2016-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号:US11659770B2
公开(公告)日:2023-05-23
申请号:US17004637
申请日:2020-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dae-Shik Kim , Jeong-Heon Park , Gwan-Hyeob Koh
CPC classification number: H01L43/12 , G11C11/161 , H01L27/228 , H01L29/41791 , H01L43/02 , H01L43/08
Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
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公开(公告)号:US10249820B2
公开(公告)日:2019-04-02
申请号:US15366574
申请日:2016-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kwang-Woo Lee , Dae-Hwan Kang , Gwan-Hyeob Koh
Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.
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公开(公告)号:US20180247978A1
公开(公告)日:2018-08-30
申请号:US15964493
申请日:2018-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: KYU-RIE SIM , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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公开(公告)号:US20170244031A1
公开(公告)日:2017-08-24
申请号:US15296423
申请日:2016-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JI-HYUN Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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