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    CHANNEL CODING FRAMEWORK FOR 802.11AY AND LARGER BLOCK-LENGTH LDPC CODES FOR 11AY WITH 2-STEP LIFTING MATRICES AND IN-PLACE PROPERTY
    2.
    发明申请
    CHANNEL CODING FRAMEWORK FOR 802.11AY AND LARGER BLOCK-LENGTH LDPC CODES FOR 11AY WITH 2-STEP LIFTING MATRICES AND IN-PLACE PROPERTY 审中-公开

    公开(公告)号：US20170134050A1

    公开(公告)日：2017-05-11

    申请号：US15294612

    申请日：2016-10-14

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Shadi Abu-Surra ,  Eran Pisek ,  Thomas Henige ,  Rakesh Taori

    IPC: H03M13/11 ,  H04L1/00 ,  H03M13/00 ,  H04B7/04

    Abstract: Methods and apparatuses for coding a codeword. An apparatus for decoding the codeword includes a memory configured to receive the codeword encoded based on a low-density parity check (LDPC) code H-matrix and a two-step lifting matrix and processing circuitry configured to decode the received codeword. An apparatus for encoding the codeword includes memory configured to store information bits to be encoded into the codeword and processing circuitry configured to encode the codeword based on based on a LDPC code H-matrix and a two-step lifting matrix. A code length of the LDPC code H-matrix lifted by the two-step lifting matrix is an integer multiple of 672 bits. The LDPC code block H-matrix may be an IEEE 802.11ad standard LDPC coding matrix. The two-step lifting matrix can be one of a plurality of two-step lifting matrices to generate a family of LDPC codes.

    SC-LDPC CODES FOR WIRELESS COMMUNICATION SYSTEMS: FRAMEWORK AND ZIGZAG-WINDOW DECODER
    3.
    发明申请
    SC-LDPC CODES FOR WIRELESS COMMUNICATION SYSTEMS: FRAMEWORK AND ZIGZAG-WINDOW DECODER 有权
    无线通信系统的SC-LDPC编码：框架和ZIGZAG-WINDOW解码器

    公开(公告)号：US20160164538A1

    公开(公告)日：2016-06-09

    申请号：US14823744

    申请日：2015-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shadi Abu-Surra ,  Eran Pisek ,  Sridhar Rajagopal ,  Rakesh Taori

    IPC: H03M13/11

    CPC classification number: H03M13/1128 ,  H03M13/1111 ,  H03M13/1154 ,  H03M13/116 ,  H03M13/1177 ,  H03M13/618 ,  H03M13/6306 ,  H03M13/6362

    Abstract: A receiver, such as a mobile station or base station, includes a sliding window-decoder. An antenna in the receiver is configured to receive a protograph-based spatially coupled low density parity check (SC-LDPC) code from a transmitter. The sliding window-decoder is configured to perform a SC-LDPC decoding operation on the SC-LDPC code using a sliding window. The SC-LDPC code includes a parity check matrix. The sliding window includes a subset of protograph sections on which decoding calculations are iteratively performed. The sliding window-decoder performs a stopping rule configured to cease the decoding calculations as a function of a syndrome of one or more check nodes (CNs) in the sliding window.

    Abstract translation: 诸如移动站或基站的接收机包括滑动窗口解码器。 接收机中的天线被配置为从发射机接收基于原理图的空间耦合低密度奇偶校验（SC-LDPC）码。 滑动窗口解码器被配置为使用滑动窗对SC-LDPC码执行SC-LDPC解码操作。 SC-LDPC码包括奇偶校验矩阵。 滑动窗口包括迭代执行解码计算的原型部分的子集。 滑动窗口解码器执行停止规则，其配置为在滑动窗口中作为一个或多个检查节点（CN）的综合征的函数停止解码计算。

    METHOD AND APPARATUS OF QC-LDPC CONVOLUTIONAL CODING AND LOW-POWER HIGH THROUGHPUT QC-LDPC CONVOLUTIONAL ENCODER AND DECODER
    4.
    发明申请
    METHOD AND APPARATUS OF QC-LDPC CONVOLUTIONAL CODING AND LOW-POWER HIGH THROUGHPUT QC-LDPC CONVOLUTIONAL ENCODER AND DECODER 有权
    QC-LDPC转换编码和低功耗高速率QC-LDPC转换编码器和解码器的方法与装置

    公开(公告)号：US20130086455A1

    公开(公告)日：2013-04-04

    申请号：US13625656

    申请日：2012-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eran Pisek

    IPC: H03M13/13

    CPC classification number: H03M13/1154 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/3746 ,  H03M13/4138 ,  H03M13/6502 ,  H03M13/658

    Abstract: A low-density parity check (LDPC) encoder and input configured to receive an incoming signal stream. The encoder generates, from a block code H-matrix comprising a data portion and a parity check portion, a continuous H-matrix by concatenating the data portion into successive, recurring, data blocks that are separated by a specified symbol interval, and performs LDPC encoding of each data portion using the parity check portion associated with the data portion using its associated parity check portion. Additionally, a Trellis-based low-density parity check (LDPC) decoder configured to receive an encoded stream and decode the received signal to recover the signal stream.

    Abstract translation: 低密度奇偶校验（LDPC）编码器和被配置为接收输入信号流的输入。 编码器从包括数据部分和奇偶校验部分的块代码H矩阵生成连续的H矩阵，将数据部分连接成以指定符号间隔分隔的连续的循环数据块，并执行LDPC 使用其相关联的奇偶校验部分使用与数据部分相关联的奇偶校验部分对每个数据部分进行编码。 另外，基于网格的低密度奇偶校验（LDPC）解码器被配置为接收编码流并对接收到的信号进行解码以恢复信号流。

    XF erasure code for distributed storage systems
    6.
    发明授权
    XF erasure code for distributed storage systems 有权

    公开(公告)号：US10073738B2

    公开(公告)日：2018-09-11

    申请号：US15017389

    申请日：2016-02-05

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Xiaoqing Fan ,  Eran Pisek ,  Shadi Abu-Surra

    IPC: G06F11/10 ,  H03M13/15 ,  H04L29/08

    CPC classification number: G06F11/1088 ,  H03M13/1515 ,  H03M13/154 ,  H04L67/1097

    Abstract: An encoding apparatus includes a processor and a communication interface operably coupled to a distributed storage system (DSS) that includes n storage device nodes. The processor is coupled to the communication interface, and configured to encode the nodes according to an XF erasure code by: dividing a number of symbols of original data into k data packets; selecting k of the storage device nodes to store the k data packets and n−k other storage device nodes to store parity packets; outputting the k data packets to the k selected storage device nodes; obtaining an XF code generator matrix; generating n−k parity packets according to a function of the k data packets and the XF code generator matrix; and outputting the n−k parity packets to each of the n−k other storage device nodes.

    CODED MODULATION ARCHITECTURE USING SPARSE REGRESSION CODES
    8.
    发明申请
    CODED MODULATION ARCHITECTURE USING SPARSE REGRESSION CODES 有权
    使用稀疏回归代码编码调制架构

    公开(公告)号：US20170054453A1

    公开(公告)日：2017-02-23

    申请号：US15004815

    申请日：2016-01-22

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Muryong Kim ,  Eran Pisek ,  Shadi Abu-Surra

    IPC: H03M13/27 ,  H04L1/00 ,  H04B7/06

    CPC classification number: H04L1/0045 ,  H03M13/1102 ,  H03M13/1191 ,  H04B7/0615 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0058

    Abstract: A communication system is configured to use coded modulation architecture using sparse regression codes. A transmitter includes a plurality of antenna and processing circuitry configured to: divide a data signal into a plurality of layers, allocate power individually to each of the plurality layers, encode a subset of the plurality of layers, the subset comprising a number of layers less than the whole, and interleave the subset of the plurality of layers. A receiver includes a plurality of antenna and processing circuitry configured to divide a received data signal into a plurality of layers and perform layer-by-layer decoding on the received data and control signals.

    Abstract translation: 通信系统被配置为使用使用稀疏回归代码的编码调制架构。 发射机包括多个天线和处理电路，其被配置为：将数据信号划分为多个层，分别分配给多个层中的每个层的功率，编码多个层的子集，所述子集包括多个层 并且交织多个层的子集。 接收机包括多个天线和处理电路，其被配置为将接收到的数据信号划分成多个层，并对所接收的数据和控制信号执行逐层解码。

    Method and apparatus to enable low power synchronization for large bandwidth wireless LAN systems
    9.
    发明授权
    Method and apparatus to enable low power synchronization for large bandwidth wireless LAN systems 有权

    公开(公告)号：US10194388B2

    公开(公告)日：2019-01-29

    申请号：US14579740

    申请日：2014-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sridhar Rajagopal ,  Shadi Abu-Surra ,  Eran Pisek

    IPC: H04W52/02 ,  H04W56/00 ,  H04W28/20 ,  H04W84/12

    Abstract: In a packet-based communication system, a transmitter and a receiver implement low power synchronization techniques. The transmitter transmits a packet that includes a two-part preamble. A first part of the two-part preamble is transmitted at a first reduced bandwidth that is smaller than a second bandwidth of the channel, and at least one of a second part of the two-part preamble and another portion of the packet is transmitted at the second bandwidth of the channel. The receiver includes an interleaved analog-to-digital converter (ADC) including multiple sub-ADCs. The receiver turns on a first subset of the multiple sub-ADCs during an idle listening period, and turns on a second subset of the multiple sub-ADCs upon detection of a completion of the first part of the two-part preamble, wherein the first subset of the multiple sub-ADCs is less than the second subset of the multiple sub-ADCs.

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