公开(公告)号：US20250124985A1

公开(公告)日：2025-04-17

申请号：US18988592

申请日：2024-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Hee Cho ,  Ji Sung Byun ,  Dong Eun Shin

IPC: G11C16/10 ,  G06N20/00 ,  G11C16/08 ,  G11C16/34

Abstract: A storage system includes a non-volatile memory (NVM) device, having a memory cell array, and a storage controller. The storage controller receives a write command and data from a host and controls the NVM device to write the data in the memory cell array. Additionally, the storage controller determines a memory region of the memory cell array in which the data will be written, clusters a plurality of word lines into a plurality of groups on the basis of feature information of the plurality of word lines, rearranges an access order in units of groups according to the feature information, and accesses the word lines in the rearranged order to write the data in the memory region.

公开(公告)号：US11435947B2

公开(公告)日：2022-09-06

申请号：US16745451

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Dong Eun Shin ,  Yong Chan Jo

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/54

Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.

公开(公告)号：US12014772B2

公开(公告)日：2024-06-18

申请号：US17847948

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Eun Shin ,  Jeong Uk Kang ,  Hyun Jin Choi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an Nth programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.

公开(公告)号：US12211553B2

公开(公告)日：2025-01-28

申请号：US17939021

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Hee Cho ,  Ji Sung Byun ,  Dong Eun Shin

IPC: G11C11/00 ,  G06N20/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

Abstract: A storage system includes a non-volatile memory (NVM) device, having a memory cell array, and a storage controller. The storage controller receives a write command and data from a host and controls the NVM device to write the data in the memory cell array. Additionally, the storage controller determines a memory region of the memory cell array in which the data will be written, clusters a plurality of word lines into a plurality of groups on the basis of feature information of the plurality of word lines, rearranges an access order in units of groups according to the feature information, and accesses the word lines in the rearranged order to write the data in the memory region.

公开(公告)号：US12019918B2

公开(公告)日：2024-06-25

申请号：US17883261

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Dong Eun Shin ,  Yong Chan Jo

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0661 ,  G06F3/0673 ,  G06F9/485 ,  G06F9/546

Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.