公开(公告)号：US09899411B2

公开(公告)日：2018-02-20

申请号：US15414345

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L21/8247 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/10 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

公开(公告)号：US09136120B2

公开(公告)日：2015-09-15

申请号：US14573845

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Young Taek Hong ,  Jinuk Lee ,  Junghun Lim ,  Jaewan Park ,  Chanjin Jeong ,  Hoon Han ,  Seonghwan Park ,  Yanghwa Lee ,  Sang Won Bae ,  Daehong Eom ,  Byoungmoon Yoon ,  Jihoon Jeong ,  Kyunghyun Kim ,  Kyounghwan Kim ,  ChangSup Mun ,  Se-Ho Cha ,  Yongsun Ko

IPC: H01L21/302 ,  H01L21/02 ,  C09K13/04 ,  C23F1/16 ,  C09K13/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/02658 ,  C09K13/04 ,  C09K13/06 ,  C23F1/16 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

公开(公告)号：US09972638B2

公开(公告)日：2018-05-15

申请号：US14621568

申请日：2015-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghae Lee ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC: H01L21/8238 ,  H01L27/11582 ,  H01L29/78 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

公开(公告)号：US09076879B2

公开(公告)日：2015-07-07

申请号：US13974122

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20150104932A1

公开(公告)日：2015-04-16

申请号：US14573845

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Young Taek Hong ,  Jinuk Lee ,  Junghun Lim ,  Jaewan Park ,  Chanjin Jeong ,  Hoon Han ,  Seonghwan Park ,  Yanghwa Lee ,  Sang Won Bae ,  Daehong Eom ,  Byoungmoon Yoon ,  Jihoon Jeong ,  Kyunghyun Kim ,  Kyounghwan Kim ,  ChangSup Mun ,  Se-Ho Cha ,  Yongsun Ko

IPC: H01L21/02 ,  H01L27/115 ,  C09K13/06

CPC classification number: H01L21/02658 ,  C09K13/04 ,  C09K13/06 ,  C23F1/16 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Abstract translation: 提供蚀刻组合物。 蚀刻组合物包括磷酸，铵离子和硅化合物。 硅化合物包括硅原子，具有与硅原子结合的氨基的原子团以及与硅原子结合的至少两个氧原子。 还提供了利用蚀刻组合物的方法。

公开(公告)号：US09559111B2

公开(公告)日：2017-01-31

申请号：US14790969

申请日：2015-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20150348799A1

公开(公告)日：2015-12-03

申请号：US14824786

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Young Taek Hong ,  Jinuk Lee ,  Junghun Lim ,  Jaewan Park ,  Chanjin Jeong ,  Hoon Han ,  Seonghwan Park ,  Yanghwa Lee ,  Sang Won Bae ,  Daehong Eom ,  Byoungmoon Yoon ,  Jihoon Jeong ,  Kyunghyun Kim ,  Kyounghwan Kim ,  ChangSup Mun ,  Se-Ho Cha ,  Yongsun Ko

IPC: H01L21/311 ,  H01L27/115 ,  H01L29/66 ,  C09K13/06

CPC classification number: H01L29/7926 ,  C09K13/04 ,  C09K13/06 ,  C23F1/16 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Abstract translation: 提供蚀刻组合物。 蚀刻组合物包括磷酸，铵离子和硅化合物材料。 硅化合物材料包括硅原子，选自氮原子，磷原子和与硅原子结合的硫原子中的至少一种，以及与硅原子结合的至少两个氧原子。 还提供了利用蚀刻组合物的方法。

公开(公告)号：US09368647B2

公开(公告)日：2016-06-14

申请号：US14824786

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Young-Taek Hong ,  Jinuk Lee ,  Junghun Lim ,  Jaewan Park ,  Chanjin Jeong ,  Hoon Han ,  Seonghwan Park ,  Yanghwa Lee ,  Sang Won Bae ,  Daehong Eom ,  Byoungmoon Yoon ,  Jihoon Jeong ,  Kyunghyun Kim ,  Kyounghwan Kim ,  ChangSup Mun ,  Se-Ho Cha ,  Yongsun Ko

IPC: C09K13/04 ,  H01L29/792 ,  C09K13/06 ,  C23F1/16 ,  H01L21/311 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/7926 ,  C09K13/04 ,  C09K13/06 ,  C23F1/16 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Abstract translation: 提供蚀刻组合物。 蚀刻组合物包括磷酸，铵离子和硅化合物材料。 硅化合物材料包括硅原子，选自氮原子，磷原子和与硅原子结合的硫原子中的至少一种，以及与硅原子结合的至少两个氧原子。 还提供了利用蚀刻组合物的方法。