公开(公告)号：US09859288B2

公开(公告)日：2018-01-02

申请号：US14700404

申请日：2015-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC: H01L21/764 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11517 ,  H01L29/06 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

公开(公告)号：US09685519B2

公开(公告)日：2017-06-20

申请号：US14728328

申请日：2015-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Na-Ra Kim ,  Seung-Hwan Kim ,  Sung-Hee Lee ,  Dae-Sin Kim ,  Ji-Young Kim ,  Dong-Soo Woo

IPC: H01L29/66 ,  H01L21/332 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/76229 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.

公开(公告)号：US09082850B2

公开(公告)日：2015-07-14

申请号：US13959765

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Na-Ra Kim ,  Seung-Hwan Kim ,  Sung-Hee Lee ,  Dae-Sin Kim ,  Ji-Young Kim ,  Dong-Soo Woo

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/4236 ,  H01L21/76229 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.

Abstract translation: 半导体器件包括在衬底中的场区域以限定有源区域，栅极沟槽包括跨过有源区域设置的有源沟槽和场区域中的场沟槽，以及填充栅极沟槽并在第一方向上延伸的字线。 字线包括占据有源沟槽的有源栅电极和占据场沟的场栅电极。 设置在彼此相邻并且在其间具有一个字线的有源区之间的每个场栅电极的底表面被设置在比有源栅电极的底表面更高的电平。

公开(公告)号：US20150236028A1

公开(公告)日：2015-08-20

申请号：US14700404

申请日：2015-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Woo OH ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

Abstract translation: 一种半导体器件，包括其中形成有沟槽的衬底，多个栅极结构，隔离层图案和绝缘层间图案。 衬底包括由沟槽限定的多个有源区，并在第二方向彼此间隔开。 每个有源区域沿着基本上垂直于第二方向的第一方向延伸。 多个栅极结构中的每一个包括依次层叠在基板上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。 隔离层图案形成在沟槽中。 第一隔离层图案在至少一对相邻的浮置栅极的侧壁之间具有至少一个第一气隙。 绝缘层间图案形成在栅极结构之间，第一绝缘层间图案沿第二方向延伸。