公开(公告)号：US09859288B2

公开(公告)日：2018-01-02

申请号：US14700404

申请日：2015-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Woo Oh ,  Dae-Sin Kim ,  Young-Kwan Park ,  Keun-Ho Lee ,  Seon-Young Lee

IPC: H01L21/764 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11517 ,  H01L29/06 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0653

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.