公开(公告)号：US20210202456A1

公开(公告)日：2021-07-01

申请号：US17023533

申请日：2020-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Bum KIM ,  Sung Hoon KIM ,  Dae Seok BYEON

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00

Abstract: A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

公开(公告)号：US20200152276A1

公开(公告)日：2020-05-14

申请号：US16744763

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C5/14 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

公开(公告)号：US20190287629A1

公开(公告)日：2019-09-19

申请号：US16154111

申请日：2018-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  II Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C16/28 ,  G11C11/56 ,  G06F11/10 ,  G06F3/06

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20210193679A1

公开(公告)日：2021-06-24

申请号：US16993570

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Chan Ho KIM ,  Kyung Hwa YUN ,  Dae Seok BYEON ,  Chi Weon YOON

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

公开(公告)号：US20210158877A1

公开(公告)日：2021-05-27

申请号：US17168613

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

IPC: G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

公开(公告)号：US20220190131A1

公开(公告)日：2022-06-16

申请号：US17409681

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Min KO ,  Myung Hun LEE ,  Pan Suk KWAK ,  Dae Seok BYEON

IPC: H01L29/423 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.

公开(公告)号：US20220084859A1

公开(公告)日：2022-03-17

申请号：US17536551

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ick SON ,  Dae Seok BYEON ,  Bong Soon LIM

IPC: H01L21/67 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C8/14 ,  G11C7/18 ,  H01L25/18

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

公开(公告)号：US20200265908A1

公开(公告)日：2020-08-20

申请号：US16865675

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  Il Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C27/00 ,  G11C16/28 ,  G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G06F11/10

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20220172786A1

公开(公告)日：2022-06-02

申请号：US17675085

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

IPC: G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56 ,  G11C16/24

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

公开(公告)号：US20210367792A1

公开(公告)日：2021-11-25

申请号：US17161124

申请日：2021-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAN HO KIM ,  Dae Seok BYEON

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/14 ,  G11C16/04

Abstract: A nonvolatile memory device with high security is provided. A nonvolatile memory device comprises a memory cell array and a secure module, wherein the secure module is configured to process first data including information about the nonvolatile memory device stored in the memory cell array to generate a first password key, process second data including information about the nonvolatile memory device stored in the memory cell array to generate a second password key, generate a public key and a secret key by a public-key cryptography algorithm, using the first password key and the second password key, and provide the first password key, the second password key, the public key, and the secret key to the memory cell array, the memory cell array is configured to store the first password key, the second password key, the public key, and the secret key, the second data is different from the first data, a value of the first password key value and a value of the second password key are prime numbers, and the public key is provided to a host connected to the nonvolatile memory device.