公开(公告)号：US20230411472A1

公开(公告)日：2023-12-21

申请号：US18144618

申请日：2023-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongik KIM ,  Chunghwan SHIN ,  Jaemoon LEE ,  Seongdong LIM

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device includes a substrate; an active region extending in a first direction on the substrate; a gate structure extending in a second direction on the substrate and including a gate electrode; a source/drain region provided on the active region on at least one side of the gate structure; an interlayer insulating layer covering the gate structure; a first contact structure connected to the source/drain region on at least one side of the gate structure; and a gate contact structure passing at least partially through the interlayer insulating layer and connected to the gate electrode, wherein the gate contact structure includes: a first layer including a conductive material; a second layer provided on the first layer, spaced apart from the interlayer insulating layer by the first layer, and including first impurities; and a third layer provided on the second layer and including second impurities.

公开(公告)号：US20240170546A1

公开(公告)日：2024-05-23

申请号：US18216640

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongheum CHOI ,  Chunghwan SHIN ,  Rakhwan Kim ,  Yeji Song

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/66795

Abstract: A semiconductor device includes: an active fin disposed on a substrate and protruding from an upper surface of the substrate; a gate structure disposed on the active fin; a source/drain layer disposed on a portion of the active fin adjacent to the gate structure; an ohmic contact pattern on the source/drain layer; and a contact plug disposed on an upper surface of the ohmic contact pattern, wherein the contact plug includes: a conductive structure including a metal; and a barrier pattern covering a lower surface and a sidewall of the conductive structure, wherein a thickness of the barrier pattern is equal to or less than about 10 Å, and wherein a maximum diameter of a grain of the metal included in the conductive structure is in a range of about 8 nn to about 15 nm.

公开(公告)号：US20240178061A1

公开(公告)日：2024-05-30

申请号：US18339569

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghee SEO ,  Rakhwan KIM ,  Jeongik KIM ,  Chunghwan SHIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76876 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53266

Abstract: An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

公开(公告)号：US20240339395A1

公开(公告)日：2024-10-10

申请号：US18494183

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungchul KANG ,  Rakhwan KIM ,  Jeongik KIM ,  Chunghwan SHIN ,  Daeun KIM ,  Seongdong LIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate contact structure electrically connected to the outer electrode. The gate contact structure may include a lower gate contact on a top surface of the outer electrode and an upper gate contact on the lower gate contact. The lower gate contact may include a first liner pattern, a first filling pattern on the first liner pattern, and a nucleation pattern between the first liner pattern and the first filling pattern. The upper gate contact may not include the nucleation pattern.

公开(公告)号：US20200381528A1

公开(公告)日：2020-12-03

申请号：US16998493

申请日：2020-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Heonbok LEE ,  Chunghwan SHIN ,  Yongsuk CHAI ,  Sangjin HYUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.